1 Fundamental Semiconductor Concepts

Let's dive into the fundamental concepts that make modern semiconductors work, focusing on device structures, materials, dielectrics, and doping. These are the building blocks for any fab you might build, whether on Earth or eventually on the Moon.

Core concepts: transistors, gates, source and drain regions, channels, gate length, pitch, FinFETs, Gate-All-Around transistors, planar transistors, Silicon-on-Insulator. Materials: silicon, copper, tungsten, aluminum, gold, titanium, zirconium, tantalum, diamond, graphene. Dielectrics: silicon dioxide, high-k dielectrics, aluminum oxide, silicon nitride. Doping: n-type, p-type, ion implantation, gas-phase doping, junctions, carriers, mobility.

Device Structures

Let's start with the transistor, the basic switching element in every digital circuit. A MOSFET, or metal oxide semiconductor field effect transistor, has four key parts: the source and drain regions where current flows in and out, the channel between them where current actually travels, and the gate electrode that sits above the channel and controls whether current flows. The gate is separated from the channel by a thin insulating layer called the gate dielectric.

When we talk about a 2-nanometer node, we're really talking about the gate length, the physical dimension of the gate along the direction of current flow. But here's a subtlety: at the 2-nanometer node, the actual physical gate length is closer to 12 nanometers. The "2 nanometer" refers to the equivalent electrical behavior due to quantum mechanical effects. This matters because as transistors shrink, short-channel effects, drain-induced barrier lowering, and quantum tunneling start to dominate.

Pitch is different from feature size. Pitch means the center-to-center spacing between repeated features, typically about one and a half to two times the minimum feature size. At TSMC's N3 node, the metal pitch is around 48 nanometers, while N2 will be around 40 nanometers. This metal pitch often determines what we call a technology node more than the gate length itself.

The evolution of transistor architectures tells an important story. Planar transistors, used before the 22-nanometer node, are simple and flat. But below 30-nanometer gate lengths, they suffered from poor electrostatic control. The gate couldn't effectively turn the channel off, leading to high leakage current. Intel introduced FinFETs at their 22-nanometer node in 20 11. A FinFET uses a vertical silicon fin with the gate wrapped around three sides, giving much better control. This reduced leakage by about 10 times compared to planar designs.

Now we're moving to Gate-All-Around or GAA transistors, also called nanosheets. Samsung launched these at 3 nanometers in 20 22, and TSMC's N2 node coming in 20 25 will use them. In GAA, the gate completely wraps around horizontal silicon nanosheets, giving even better electrostatic control. The width of these sheets can be tuned to optimize for either performance or density. Looking ahead, we'll see forksheet designs with separate n-type and p-type regions, and CFET, which stacks complementary transistors vertically.

Silicon-on-Insulator, or SOI, deserves mention. This uses a buried oxide layer beneath the active silicon. The benefits include about 30 percent lower parasitic capacitance and immunity to a failure mode called latch-up. Fully-depleted SOI, or FD-SOI, from companies like GlobalFoundries at 22 nanometers, competed with FinFETs by allowing dynamic performance tuning through body biasing. The downside is cost: SOI wafers run one thousand to two thousand dollars compared to one hundred to three hundred for bulk wafers. On the Moon, making SOI is complicated because you need oxygen for the buried oxide layer, or you need wafer bonding capabilities. You might instead back-grind bulk wafers to thin layers, but that makes them mechanically fragile.

For FinFETs specifically, the fin width is typically 5 to 8 nanometers, and the height is 40 to 60 nanometers. Making these requires patterning bulk silicon using either self-aligned quadruple patterning or EUV lithography, then etching with anisotropic reactive ion etching. Challenges include fin roughness causing variation in how easily current flows, and the high aspect ratio complicating doping. Ion implantation has a shadowing problem with tall fins, so you need plasma doping or in-situ doped epitaxy instead.

If you're building a Western fab to compete with TSMC, FinFET technology is mature. You can license designs from Intel or Samsung. Key talent is in Oregon where Intel is based, Austin for Samsung, and Albany Nanotech in New York. Moving to GAA is more complex: you need to do a selective etch to release the nanosheets by removing sacrificial silicon germanium layers, form inner spacers, and ensure the gate wraps around completely. This requires very conformal atomic layer deposition, or ALD.

Materials

Silicon is the foundation. You start with metallurgical-grade silicon at 98 percent purity, made by reducing quartz, silicon dioxide, with carbon. That costs about two dollars per kilogram. To get electronic-grade polysilicon at 11-nines purity, you use the Siemens process, depositing silicon from trichlorosilane gas. This costs 15 to 30 dollars per kilogram. Then you grow single-crystal ingots using the Czochralski method, where you pull a seed crystal slowly from molten silicon. Western suppliers include Hemlock in the US and Wacker in Germany.

On the Moon, silicon dioxide makes up about 45 percent of the regolith by mass. You can do carbothermal reduction, heating silicon dioxide with carbon to produce silicon and carbon dioxide. The challenge is you'd need to import carbon, or process other minerals like anorthite or ilmenite. The Siemens process needs chlorine, which is scarce on the Moon. Alternatives include direct electrolysis or using metals like calcium or magnesium to reduce silicon dioxide. Growing ingots in one-sixth gravity reduces convection, which actually helps with defect control, but you'd need to redesign the pulling equipment.

Copper replaced aluminum for interconnects, the wiring between transistors, back in 19 97 when IBM introduced it. Copper has lower electrical resistivity, 1.68 micro-ohm-centimeters versus 2.65 for aluminum, and better resistance to a failure mode called electromigration where metal atoms gradually move under current stress. The damascene process is used: you etch a trench in the insulating layer, deposit a thin barrier layer of tantalum or tantalum nitride, about 2 to 3 nanometers thick, to prevent copper from diffusing into silicon, then fill with copper by electroplating, and polish flat with chemical-mechanical polishing, or CMP.

At pitches below 10 nanometers, the barrier thickness becomes a problem. It takes up 40 percent of the cross-section, increasing resistance. Ruthenium is being explored as a barrierless metal, but its bulk resistivity is higher. At the nanoscale, grain boundary scattering dominates. Lines under 10 nanometers can show 3 to 5 times higher resistivity than bulk copper.

For a Western fab, copper electroplating vendors include Atotech and Enthone. Barrier ALD equipment comes from Applied Materials and Lam Research. On the Moon, you'd extract copper from lunar basalt, which contains about 100 to 200 parts per million. Electroplating traditionally needs aqueous chemistry, which is challenging in vacuum. Dry alternatives include physical vapor deposition, or PVD, with reflow, or chemical vapor deposition using precursors like copper hexafluoroacetylacetonate. Working in vacuum eliminates oxidation, so copper might not need passivation if it never sees atmosphere.

Tungsten is used for contacts and vias, the small vertical connections under 50 nanometers in diameter. It's deposited by CVD from tungsten hexafluoride gas. The reaction is tungsten hexafluoride plus hydrogen producing tungsten metal and hydrogen fluoride. A titanium nitride liner prevents the fluorine from attacking silicon. Tungsten's resistivity is 5 to 10 micro-ohm-centimeters, higher than copper, but acceptable for short vertical paths. On the Moon, fluorine is scarce, so you might use chloride precursors instead, or reduce tungsten oxides directly, though tungsten minerals are unlikely on the Moon and would need to be imported.

Aluminum is the legacy interconnect metal, still used for top-level bonding pads. It's deposited by PVD sputtering. Alloys with 0.5 to 2 percent copper and 1 percent silicon improve electromigration resistance. It's cheap at 2 to 5 dollars per kilogram. On the Moon, aluminum is abundant in anorthite, a mineral with the formula calcium aluminum silicate. Lunar regolith contains about 14 percent aluminum oxide. You can extract it using molten salt electrolysis or processes similar to the Bayer process with sodium hydroxide, though sodium would need to be imported initially.

Barrier metals like tantalum and titanium prevent copper or tungsten from diffusing into silicon, which would create deep-level traps that kill device performance. Tantalum or tantalum nitride is most common, deposited by PVD or ALD. ALD can achieve conformal layers under 2 nanometers using precursors like tantalum pentachloride and ammonia. These metals come from ores: tantalite for tantalum, ilmenite for titanium. On the Moon, ilmenite is abundant in the lunar maria at 10 to 18 percent. You can extract titanium by carbothermal or hydrogen reduction. Tantalum is rare and would need to be imported.

Gold is used for wire bonding and flip-chip solder bumps. It costs about 60 thousand dollars per kilogram and has a risk of migration, so it's limited to packaging areas. On the Moon, you'd import it, as there are only trace concentrations. Aluminum bonding with ultrasonic wedge bonders is an alternative.

Getters are reactive metals like titanium or zirconium that absorb residual gases like water, oxygen, and nitrogen inside vacuum packages. This maintains pressure below 10 to the minus 6 Torr over the device lifetime. They're activated by heating to 300 to 400 degrees Celsius after sealing. On the Moon, titanium is abundant but zirconium is scarce. Interestingly, vacuum packages sealed in lunar ultra-high vacuum might not need getters at all if they're never exposed to Earth's atmosphere. Cold-welded vacuum packages would be inherently cleaner.

Diamond and graphene are explored for thermal management. Diamond has thermal conductivity around 2000 watts per meter-kelvin, graphene around 3000 to 5000, compared to silicon's 150. Diamond films are grown by CVD from methane and hydrogen plasma. Challenges include stress, adhesion, and surface roughness. Graphene is grown by CVD on copper foil, then transferred to the device, which risks contamination. On the Moon, carbon is a critical import bottleneck. An alternative is using the Moon's natural vacuum for direct radiative heat transport to radiators, since there's no convection or conduction atmosphere.

Dielectrics

Dielectrics are insulators. Silicon dioxide is the classic one. It forms naturally on silicon in the presence of oxygen or water as a native oxide about 2 nanometers thick. Thermal oxidation, heating silicon in dry oxygen at 900 to 1100 degrees Celsius, grows thicker layers for isolation and gate dielectrics. The reaction happens at the silicon-silicon dioxide interface following the Deal-Grove model. Silicon dioxide has excellent interface quality with very low defect density, fewer than 10 to the 10 per square centimeter. Its dielectric constant, k, is about 3.9. But it breaks down at about 1 nanometer equivalent oxide thickness due to quantum tunneling.

High-k dielectrics replaced silicon dioxide at the 45-nanometer node. Hafnium dioxide has k around 25, aluminum oxide around 9, zirconium dioxide around 25. These allow physically thicker layers for the same electrical thickness, reducing gate leakage by 100 times. Hafnium dioxide is deposited by ALD using precursors like tetrakis dimethylamino hafnium and water at 300 degrees Celsius. Challenges include mobility degradation from remote phonon scattering and threshold voltage instability from charge trapping. You also need metal gates like titanium nitride or tantalum nitride instead of polysilicon to avoid Fermi-level pinning. Western suppliers of precursors include Entegris and Versum. On the Moon, hafnium is rare and would need importing. Aluminum oxide from lunar anorthite is an alternative, with lower k but acceptable for analog applications.

Inter-layer dielectrics, or ILD, insulate the metal wiring layers. Low-k materials with k below 3 reduce parasitic capacitance. Silicon oxycarbide with hydrogen, deposited by plasma-enhanced CVD from organosilane precursors, has k around 2.5 to 3.0. Porous versions reach k around 2.0 to 2.5 by introducing voids, but they're mechanically weak. On the Moon, hydrogen and carbon are critical and need closed-loop recycling. An exciting possibility is using vacuum itself as the dielectric. If devices are processed and sealed entirely in vacuum, you could have interconnects with k equal to 1, a radical simplification.

Silicon nitride is used for passivation, encapsulating devices to prevent moisture and ion ingress. It's deposited by plasma-enhanced or low-pressure CVD from silane and ammonia. Low-pressure CVD at 750 to 900 degrees gives higher quality but is slower. On the Moon, nitrogen would need to be imported and recycled. But if devices are sealed in lunar ultra-high vacuum from the start, passivation might be completely unnecessary. Cold-welded metal lids in vacuum would eliminate the need for polymer or nitride coatings.

Doping and Carriers

Doping means adding impurities to silicon to control its electrical conductivity. N-type silicon is doped with elements like phosphorus or arsenic that donate extra electrons. P-type is doped with boron, which accepts electrons, creating "holes" that act as positive charge carriers.

Ion implantation is the traditional method. You accelerate dopant ions to 1 to 200 kilo-electron-volts and shoot them into the silicon. Depth is controlled by energy, dose by beam current times time. This damages the crystal, so you need thermal annealing at 1000 to 1100 degrees Celsius to repair the lattice and electrically activate the dopants. For ultra-shallow junctions under 10 nanometers needed in FinFETs, you need low energies below 1 kilo-electron-volt, but beam divergence becomes a problem. Molecular ions, like boron hydride clusters, help because the boron ends up at the surface when the molecule breaks apart. Tool vendors include Applied Materials and Axcelis. On the Moon, high-energy ion beams work well in vacuum since there's no charge neutralization issue. Annealing furnaces would need vacuum or inert gas like nitrogen or argon, which would be imported.

Gas-phase doping exposes silicon to doping gases like arsine, phosphine, or diborane at 600 to 800 degrees Celsius. Diffusion drives the dopants in. Monolayer doping is a variant: you adsorb a dopant-containing molecule on an oxide surface, drive it in with rapid thermal annealing, then strip the oxide. This achieves ultra-abrupt profiles. In-situ doped epitaxy is used for FinFET source and drain regions: you grow silicon or silicon germanium selectively in CVD while flowing a doping gas. This avoids implant damage and works better for 3D structures. On the Moon, toxic hydrides are difficult to synthesize, requiring hydrogen plus arsenic or phosphorus at high temperature. Alternatives include solid-source diffusion from doped glasses, though that's slower.

Carrier physics: electrons in bulk silicon have mobility around 1400 square centimeters per volt-second, but in inversion layers near the surface, it drops to 300 to 500 due to surface roughness scattering. Holes have lower mobility, around 450. FinFET sidewalls oriented in the 110 crystal direction have higher electron mobility than 100 planar surfaces. Strain engineering using silicon germanium in the source and drain for p-type FETs, or silicon carbide for n-type, enhances mobility by 20 to 50 percent. High-k metal gates degrade mobility through remote phonon scattering and scattering from charged traps.

Junction formation requires abrupt doping changes over less than 5 nanometers for good short-channel control. This is achieved with spike annealing, ramping to 1050 degrees in 1 second then cooling immediately, or laser annealing with millisecond pulses that melt and regrow the surface. There's a trade-off between activating dopants and preventing them from diffusing. Flash annealing uses millisecond lamp pulses. On the Moon, laser annealing is advantageous since electrical power is abundant from solar. Furnace annealing would require gas handling infrastructure.

Moon-Specific Insights

The lunar surface offers ultra-high vacuum, around 10 to the minus 12 Torr. This eliminates the need for vacuum chambers during processing. Tools can be open-frame. There's no oxidation or contamination between steps. Cold welding, where clean metal surfaces bond at room temperature in ultra-high vacuum, enables vacuum packaging without traditional hermetic sealing. Devices can operate in vacuum with no dielectric breakdown from humidity, allowing higher voltage operation. Passivation layers become unnecessary. You could even route signals through vacuum with minimal capacitance, using vacuum as your dielectric with k equal to 1.

The material constraint on the Moon is volatiles: hydrogen, carbon, nitrogen, chlorine, fluorine. These are scarce and must be imported or recycled. This impacts etching gases like carbon tetrafluoride, nitrogen trifluoride, and chlorine; CVD precursors like silane and tungsten hexafluoride; and doping gases. Opportunities include developing dry etch alternatives like ion milling, solid-state diffusion sources, and metallothermal reductions that don't need volatile reagents. Metals are abundant: aluminum, titanium, and iron from regolith; silicon from silicates. Processing methods include carbothermal reduction, molten salt electrolysis, and hydrogen reduction.

Thermal management is challenging because there's no convection, only radiative cooling. Large radiators are required. But silicon processing benefits from stable, controllable temperatures. Czochralski crystal pulling with reduced convection minimizes defects, though it requires redesigned heaters.

A simplified process flow is essential. Target under 50 process steps versus the 500-plus on Earth. Strategies: use thicker structures with relaxed lithography requirements, fewer metal layers, eliminate redundant cleans and passivation. An example process: planar transistors with gas-phase doping to avoid implantation and annealing, a single copper metal layer with vacuum dielectric, and cold-welded packaging in vacuum. Applications would be radiation-hard chips for lunar infrastructure, not cutting-edge logic.

Western Fab Competitive Strategies

To compete with TSMC, which dominates through EUV lithography with 7-plus layers at N3, advanced packaging like CoWoS and SoIC, and mature yield, Western fabs need different strategies. Advantages include proximity to customers like hyperscalers and defense and supply chain security concerns.

Chiplets are one approach. Instead of a monolithic die, you disaggregate into smaller chiplets connected via high-bandwidth interposers like silicon bridges or organic substrates. This reduces yield loss because defects only affect one chiplet, and you can mix and match IP blocks. The UCIe standard from 20 22 defines die-to-die interconnect. Intel's Foveros and AMD's Infinity Fabric are examples. It's easier to start small and scale with chiplets than to master a leading-edge monolithic process immediately.

Vacuum-integrated processing is another strategy. Multi-chamber cluster tools from Applied Materials' Endura line or Lam's Coronus link deposition, etch, and clean without air exposure. Extend this concept to the entire fab: wafers never leave vacuum from bare silicon to diced chips. This eliminates cleans, passivation, and particle contamination.

Cold welding for packaging: bond metal lids or caps in vacuum via diffusion bonding of gold-gold or copper-copper at 200 to 300 degrees Celsius. This creates a hermetic seal without polymers or solders and enables vacuum-packaged chips.

Focusing on analog and RF is strategic. TSMC is optimized for digital logic. RF applications for 5G and satellite, power devices in silicon carbide and gallium nitride, and automotive applications are less mature. Gallium nitride on silicon and silicon carbide MOSFETs require specialized epitaxy and high-temperature processing. Western companies include Wolfspeed for silicon carbide wafers and IQE for gallium nitride epitaxy.

The chiplet ecosystem requires standardized interfaces like UCIe physical layer and protocol, advanced packaging where TSMC and Intel lead, and thermal management since chiplet density increases power density. Opportunities include AI-optimized chiplets for SRAM, HBM controllers, and domain-specific accelerators, plus heterogeneous integration combining silicon logic with gallium nitride RF and photonics. Western talent is in Silicon Valley for chiplet startups and Intel's Arizona and Oregon sites.

For cold welding, gold-gold thermocompression bonding is used in hybrid bonding like TSMC's SoIC. Copper-copper bonding at wafer-level enables 3D stacking. At pitches below 10 micrometers, you need surface roughness under 20 nanometers and particle-free conditions. Tools come from Applied Materials and Besi. On the Moon, ultra-high vacuum bonding is ideal with no oxide formation. For an Earth fab, vacuum packaging via cold-welded lids allows higher voltage operation and eliminates wirebond or solder reliability issues. Markets include automotive with 200-degree Celsius junction temperatures and aerospace.

Vacuum dielectric means replacing inter-layer dielectrics with air gaps or pure vacuum. Challenges include mechanical support and CMP compatibility. A hybrid approach uses sparse silicon dioxide pillars in vacuum, enabling 50 percent capacitance reduction. TSMC explored this at 7 nanometers but had yield issues. A Western opportunity is optimizing for chiplets with shorter interconnects and fewer layers, or for analog with larger geometries where vacuum integration is easier.

Keep-in-vacuum processing requires cluster tools with load-locks and robot handlers. Applied's Centura for deposition and Lam's Kiyo for etch are already multi-chamber. Extend via vacuum interconnects between tools, with wafer carriers in vacuum tunnels. Benefits include eliminating native oxide regrowth, which is critical for metal contacts, reducing defects, and skipping wet cleans. Challenges are maintenance, since opening chambers exposes them to air, and throughput due to serial processing. The opportunity is a greenfield fab designed around vacuum integration from the start, modular and expandable. Talent is at IMEC in Belgium, which pioneered cluster tools. Equipment partners could be Applied Materials and Lam for customization.

AI and Automation Opportunities

AI-driven process optimization combines TCAD simulation tools like Sentaurus or Silvaco with machine learning models to predict device performance from process parameters. Bayesian optimization explores the parameter space, such as doping profiles and annealing temperatures, faster than traditional design of experiments. For example, optimize FinFET spacer width for the speed versus leakage trade-off using neural surrogate models. Atomica, a startup running an analog and MEMS fab, uses machine learning for yield prediction. The opportunity is a foundry-as-a-service with an AI loop where customers submit designs, AI optimizes the process recipe, and rapid tapeout follows.

Automated defect inspection: optical and e-beam inspection generate terabytes per day of images. Convolutional neural networks classify defects like particles, bridges, and voids 10 times faster than human review. KLA and Applied Materials tools integrate machine learning. The opportunity is real-time defect feedback to upstream process tools, closing the loop within hours instead of days.

Mature robotics, whether humanoid or specialized, enables flexible automation. Robots can retool for new processes without hardcoded paths, with adaptive grasping for varied wafer carriers. They can service tools, replacing consumables and cleaning chambers in vacuum without shutting down the entire fab. For a lunar fab, teleoperated robots bootstrap initial infrastructure and transition to autonomy. Mini-fabs with under 10 thousand wafers per month become viable with robotic labor replacing human cleanroom workers, shifting economics toward Western high-mix, low-volume markets.

Historical and Novel Approaches

Several abandoned ideas are worth revisiting. X-ray lithography using synchrotrons offered sub-10-nanometer resolution without EUV complexity. It was abandoned due to mask cost and infrastructure. Modern compact X-ray sources using laser-plasma and ML-designed masks could revive it. On the Moon, a synchrotron in vacuum is straightforward.

Selective epitaxial growth means growing silicon or silicon germanium only in trenches, avoiding lithography and etching. It requires pristine surface selectivity, improving now with ALD inhibitors.

Electrochemical doping applies voltage in an electrolyte to inject dopants at room temperature, creating abrupt junctions. It was abandoned due to contamination but could be revisited with ultra-high vacuum electrochemistry.

Ion-cut layer transfer, like Soitec's SmartCut process for SOI, can transfer gallium nitride onto silicon or indium phosphide photonics onto silicon for heterogeneous integration. Costs are decreasing and it's becoming high-volume manufacturing ready.

Emerging research includes 2D semiconductors like molybdenum disulfide and tungsten diselenide. These atomically thin channels are immune to short-channel effects. Issues are contact resistance and synthesis scale. TSMC is exploring them for post-3-nanometer nodes. Western talent is at MIT and Stanford and is recruitable.

Cryogenic CMOS operates at 4 Kelvin for quantum computing control. Silicon mobility increases 3 times, and subthreshold swing improves. It requires redesigned interconnects using superconducting aluminum and vacuum cryostat packaging. Intel and IBM are prototyping.

Atomically precise manufacturing uses hydrogen depassivation lithography via scanning tunneling microscopes to place dopants with atomic precision. It's slow but deterministic, relevant for qubits, not high-volume manufacturing.

Direct-write e-beam using multibeam mask writers from IMS Nanofabrication achieves wafer-scale patterning without masks. It's 10 times slower than EUV but eliminates the 150-million-dollar mask cost. It's viable for prototyping and custom ASICs.

Novel ideas include vacuum transistors with nanogaps under 10 nanometers between electrodes in vacuum where electrons tunnel ballistically. There's no channel material and no doping. They're radiation-hard and high-speed. NASA explored them for space, worth revisiting for the Moon. Challenges are gap uniformity and current density.

Fluidic self-assembly mixes chiplets in liquid that self-align via shape and surface energy to an interposer, enabling massively parallel assembly. It's been demonstrated for LEDs by X-Celeprint and could extend to logic chiplets.

Thermal doping uses rapid thermal annealing to create metastable dopant supersaturation, enabling ultra-high concentrations for low-resistance contacts. It's at the research stage, but ML-optimized recipes could enable high-volume manufacturing.

For chiplets specifically, advanced packaging is dominated by TSMC and Intel. Western opportunities include organic interposers, cheaper than silicon bridges, with embedded passives like capacitors and inductors for power delivery. Promex Industries is a startup in this area. Micro-bumps with pitch under 20 micrometers using copper pillars require fine-pitch lithography, which can be adapted from the PCB industry's laser direct imaging.

Talent and Ecosystem

Key talent pools for process integration are at IMEC in Belgium, Albany Nanotech in New York, and among TSMC alumni in Austin and Portland. Device physics expertise is at Stanford, MIT, and Berkeley. Equipment talent is at Applied Materials in Santa Clara and Lam Research in Fremont. Recruiting strategies include offering equity, technical leadership roles, and unique problems like building a Moon fab. Challenges include TSMC's strong retention packages and visa restrictions for foreign talent.

Western equipment vendors include Applied Materials and Lam Research in the US, dominating deposition and etch. ASML in the Netherlands has a monopoly on EUV. Inspection comes from KLA in the US. CMP from Applied and Ebara in Japan. Non-EUV lithography from Canon in Japan and ASML. Electroplating from Atotech in the US and Germany, and Lam. The opportunity is equipment startups for vacuum-integrated processing and chiplet bonding, as incumbents are slow to innovate.

Materials supply: gases from Linde and Air Liquide in the US and EU. Precursors from Entegris and Versum, now Merck, in the US. Wafers from GlobalWafers in Taiwan with an Arizona fab planned, and Shin-Etsu in Japan. Western supply chains are weak for wafers and precursors. China dominates rare earths including hafnium and tantalum. Strategic approaches include securing tantalum and hafnium recycling, recovering metals from etch chamber cleaning, and domestic polysilicon from Hemlock.

Moon-specific talent requires cross-disciplinary expertise in semiconductors and space systems. Recruit from aerospace companies like SpaceX and Blue Origin, and from fabs. Robotics talent from Boston Dynamics and NASA JPL. In-situ resource utilization expertise from Colorado School of Mines and NASA labs.

Summary Review

Let's review the core concepts. Transistors are switches with source, drain, channel, and gate. FinFETs use vertical fins, GAA wraps the gate around nanosheets. Silicon is purified from quartz via the Siemens process. Copper interconnects need tantalum barriers and are deposited by damascene electroplating. Tungsten fills vias via CVD. High-k dielectrics like hafnium dioxide replaced silicon dioxide to reduce gate leakage. Ion implantation shoots dopants into silicon; gas-phase doping is an alternative. N-type and p-type doping create electrons and holes as carriers. Mobility is how easily carriers move.

On the Moon, ultra-high vacuum enables processing without chambers, cold welding for packaging, and vacuum dielectrics. Volatiles are scarce; metals abundant. Simplified processes target radiation-hard applications.

Western fabs can compete via chiplets, vacuum-integrated processing, cold-welded packaging, and focusing on analog and RF. AI optimizes processes and defect inspection. Robotics enable flexible automation and mini-fabs.

Historical ideas like x-ray lithography and selective epitaxy are worth revisiting. Emerging research includes 2D semiconductors, cryogenic CMOS, and atomically precise manufacturing. Novel ideas include vacuum transistors and fluidic self-assembly.

Key talent is in Silicon Valley, Oregon, Austin, Albany, and IMEC. Equipment from Applied Materials, Lam Research, ASML. Western supply chains need strengthening, especially for rare earths.New

terms and jargon: MOSFET, FinFET, GAA or gate-all-around, SOI or silicon-on-insulator, Czochralski method, damascene process, ALD or atomic layer deposition, PVD or physical vapor deposition, CVD or chemical vapor deposition, CMP or chemical-mechanical polishing, high-k dielectric, ILD or inter-layer dielectric, ion implantation, monolayer doping, UCIe standard, CoWoS and SoIC packaging, TCAD simulation, IMEC research center.