10 Electrical And Device Physics

Electrical and Device Physics in Semiconductor Manufacturing

Let's dive into the electrical and device physics underlying modern semiconductor devices. This section covers transistor physics, electrical properties, performance metrics, power and energy considerations, with insights for lunar manufacturing, Western fab strategies, and novel opportunities. We'll explore threshold voltage, drive current, leakage, on-off ratio, subthreshold slope, electrostatics, short channel effects, D-I-B-L, gate control, resistance, capacitance, inductance, conductivity, resistivity, contact resistance, sheet resistance, clock frequency, transistor count and density, F-L-O-P-S, memory bandwidth, latency, throughput, power efficiency, dynamic power, static power, energy per operation, and switching energy.

Transistor Physics Fundamentals

Threshold voltage, or V-t, is the critical voltage at which a transistor switches from off to on. For an n-channel M-O-S-F-E-T, it's determined by the flatband voltage, Fermi potential, semiconductor permittivity, doping concentration, and gate oxide capacitance. Modern nodes use multiple V-t flavors: low V-t transistors for high performance and high V-t for low leakage. Industry targets range from 0.2 to 0.5 volts for high performance, up to 0.8 volts for low power applications. At 3 nanometer nodes, process variation causes V-t distribution issues dominated by random dopant fluctuation and line edge roughness. A novel approach involves metal-ferroelectric-insulator-semiconductor structures that can achieve sub-60 millivolts per decade switching. Negative capacitance FETs exploit ferroelectric materials like hafnium-doped zirconium dioxide to overcome fundamental limits.

Drive current, or I-on, determines switching speed and overall performance. It's proportional to effective mobility, gate capacitance, channel width over length ratio, and the square of the gate voltage minus threshold voltage. Effective mobility is about 450 square centimeters per volt-second for electrons in silicon, but only 150 for holes. Strain engineering boosts mobility: tensile strain for n-channel devices achieving up to 2 gigapascals stress, compressive for p-channel. The industry uses silicon-germanium source-drain stressors and stressed liner films. Modern FinFETs and gate-all-around transistors achieve about 1 milliamp per micrometer at 0.7 volt supply. Velocity saturation limits drive current at about 10 to the 7 centimeters per second in silicon. Three-five materials like indium gallium arsenide offer higher mobility but face integration challenges. Two-dimensional materials like molybdenum disulfide promise extreme scaling but contact resistance remains problematic.

Leakage current, or I-off, causes static power consumption and is a major concern. Components include subthreshold leakage, which is exponentially dependent on threshold voltage and usually dominant, gate tunneling through thin oxides, junction leakage from band-to-band tunneling, and gate-induced drain leakage. Targets are under 100 picoamps per micrometer for high performance, under 10 for low power. Gate tunneling was addressed via high-k dielectrics like hafnium dioxide with dielectric constant about 20 versus silicon dioxide at 3.9. Equivalent oxide thickness is now about 0.7 nanometers while physical thickness is about 2 nanometers. FinFET and gate-all-around architectures improve electrostatics, reducing leakage 10 to 100 times versus planar transistors.

The on-off ratio, I-on divided by I-off, is typically 10 to the 4th to 10 to the 6th power for logic. Higher ratios enable lower power but may sacrifice performance. Tunnel FETs promise ratios of 10 to the 8th to 10 to the 10th but suffer from insufficient on-current.

Subthreshold slope, or S-S, measures how sharply a transistor turns on or off. It's the change in gate voltage needed for a tenfold change in drain current. The theoretical minimum is 60 millivolts per decade at room temperature, limited by the Boltzmann distribution—often called the Boltzmann tyranny. Steep-slope devices like tunnel FETs, negative capacitance FETs, impact ionization MOSFETs, and nanoelectromechanical switches aim to break this limit. Negative capacitance FETs using hafnium-zirconium oxide have demonstrated about 30 millivolts per decade over limited ranges, though hysteresis remains an issue.

Short channel effects occur when gate length becomes less than 5 to 10 times the depletion width, causing the drain electric field to penetrate the channel. D-I-B-L, or drain-induced barrier lowering, means drain voltage lowers the threshold voltage and increases leakage. The industry targets less than 30 millivolts change per volt of drain voltage change. Short channel effects also include V-t roll-off where threshold voltage decreases with channel length, velocity saturation, and hot carrier effects. Mitigation strategies include thin body designs—FinFETs under 10 nanometers, gate-all-around about 5 nanometers—higher channel doping which conflicts with mobility, and halo or pocket implants for retrograde doping. Gate-all-around nanosheets and nanowires offer superior electrostatics with four-sided gate control versus three-sided for FinFETs or one-sided for planar. Complementary FETs, or C-F-E-Ts, stack n-channel over p-channel transistors for higher density.

Gate control quantifies how well the gate controls the channel and is measured by the derivative of surface potential with respect to gate voltage. Ideal value is 1, but short channel effects degrade this. The Poisson equation governs the electrostatics, and a natural length scale determines scaling limits. For gate-all-around, this natural length depends on silicon permittivity, nanowire thickness, oxide thickness, and oxide permittivity. Scaling rules require the channel thickness to gate length ratio under 0.3 to 0.5.

Electrical Properties

Resistance for bulk materials is resistivity times length divided by cross-sectional area. For thin films, sheet resistance is resistivity divided by thickness, measured in ohms per square. Copper interconnects have bulk resistivity of 1.7 micro-ohm centimeters, but at sub-20 nanometer linewidths, surface and grain boundary scattering increases this to 3 to 10 micro-ohm centimeters. Alternatives include ruthenium, which is more resistant to electromigration, cobalt, graphene, and carbon nanotubes. Resistivity scales with defects, grain size, and surface roughness according to Matthiessen's rule, where total resistivity is the sum of phonon, impurity, and defect contributions.

Contact resistance at the metal-semiconductor interface is a major bottleneck at scaled nodes. It consists of specific contact resistivity divided by contact area plus spreading resistance. Targets are under 10 to the minus 9 ohm square centimeters for 3 nanometer and beyond nodes. The Schottky barrier height determines contact resistance via thermionic emission and tunneling. Fermi-level pinning in silicon limits barrier height tuning. Solutions include heavy doping above 10 to the 20th per cubic centimeter for tunneling, silicides like nickel silicide or titanium silicide, alloyed contacts, dipole engineering, and graphene interlayers. Three-five material contacts are worse than silicon due to pinning and surface states.

Capacitance includes gate capacitance—oxide capacitance times width times length—and parasitic capacitances between gate-drain, gate-source, drain-bulk, and source-bulk that affect speed. Interconnect capacitance dominates at advanced nodes, so low-k dielectrics with dielectric constants of 2.5 to 3.0, and air gaps with k equals 1, are used to reduce it. Miller capacitance, the gate-drain overlap, causes feedback and slows switching. Gate capacitance also includes quantum effects: the inversion layer capacitance in series with oxide capacitance reduces effective capacitance by 10 to 20 percent at thin oxides.

Inductance becomes relevant at multi-gigahertz frequencies and for power delivery. Parasitic inductance in interconnects causes I-R drop and ground bounce. For a simple wire, inductance depends on permeability, length, and geometry. Package inductance is typically 1 to 10 nanohenries, while on-die local interconnects are under 100 picohenries. Three-dimensional integration and chiplets require careful power delivery network design to manage L times d-i d-t noise.

Performance Metrics

Clock frequency equals 1 over the delay time, which is approximately load capacitance times supply voltage divided by on-current for a simplified model. Modern CPUs operate at 3 to 5 gigahertz, achieved via pipelining and parallelism. Frequency scaling stalled around 2005 at the 90 nanometer node due to power constraints, marking the end of Dennard scaling. Amdahl's law limits parallel efficiency. For a lunar fab, vacuum operation enables higher supply voltage without breakdown, potentially boosting frequency 20 to 50 percent, but thermal management in vacuum is challenging since there's no convection cooling.

Transistor density is currently 100 to 300 million transistors per square millimeter at 3 nanometer logic nodes. S-R-A-M memory cells limit density at about 0.02 square micrometers per bit at 3 nanometers. Gate pitch is about 50 nanometers, metal pitch 24 to 28 nanometers. Future complementary FETs could potentially double density, while monolithic three-dimensional integration could achieve 5 to 10 times density over 5 to 10 layers. Chiplets achieve effective density via heterogeneous integration with interconnect pitch now 10 to 50 micrometers; hybrid bonding enables sub-micrometer pitch.

F-L-O-P-S, or floating-point operations per second, measures compute performance. Peak F-L-O-P-S equals cores times S-I-M-D width times frequency times fused multiply-add operations per cycle. Modern G-P-Us achieve 50 to 100 teraflops for 32-bit floating point, 200 to 400 teraflops for 16-bit or B-F-16, and about 1 petaflop for 8-bit integer operations. Exascale supercomputers at 1 exaflop—10 to the 18th F-L-O-P-S—were achieved in 20 22. A-I accelerators optimize for lower precision like 4-bit or 2-bit integers. In-memory computing promises 10 to 100 times energy efficiency for matrix operations by eliminating data movement.

Memory bandwidth for H-B-M-3, high-bandwidth memory generation 3, achieves 600 to 900 gigabytes per second per stack. G-D-D-R-6-X reaches about 1 terabyte per second. The processor-memory gap persists as bandwidth scales about 1.3 times per year versus compute at 1.6 times per year. Three-dimensional integration using through-silicon vias and hybrid bonding mitigates this, with 1 terabyte per second per square millimeter demonstrated at sub-micrometer pitch. On the moon, vacuum enables direct chip-to-chip bonding without organics, simplifying three-dimensional integration.

Latency equals distance divided by signal velocity plus processing time. Signal velocity in copper is about 2 times 10 to the 8 meters per second, or 0.6 times the speed of light. Cache latency: L-1 cache about 1 nanosecond, L-2 about 3 nanoseconds, L-3 about 15 nanoseconds, D-R-A-M about 50 nanoseconds. Throughput is achieved via parallelism like pipelining and multi-core architectures. The roofline model states that performance is limited by the minimum of peak F-L-O-P-S or bandwidth times arithmetic intensity.

Power and Energy

Dynamic power equals activity factor times load capacitance times supply voltage squared times frequency. The activity factor ranges from 0 to 1 and represents the fraction of circuits switching. Dynamic power is dominant at high frequency. Reducing supply voltage is most effective since it's quadratic, but it's limited by threshold voltage variability and on-current requirements. Near-threshold computing, where supply voltage approximately equals threshold voltage around 0.5 volts, achieves minimum energy but poor performance. Clock gating reduces the activity factor. Switching energy equals load capacitance times supply voltage squared; at 3 nanometer nodes, this is about 1 femtojoule per switching event for a logic gate.

Static power equals off-current times supply voltage plus gate leakage current. This becomes significant below 22 nanometer nodes. Power gating disables unused blocks. A multi-V-t strategy uses low threshold voltage for critical paths and high threshold voltage elsewhere. Fully depleted silicon-on-insulator, or F-D-S-O-I, enables body biasing for dynamic threshold voltage adjustment. Static power comprises about 30 to 50 percent of total power at idle for modern processors.

Energy per operation is a key figure of merit for efficiency. Modern C-P-Us consume 10 to 100 picojoules per F-L-O-P, G-P-Us 1 to 10 picojoules, and specialized accelerators like T-P-Us or Cerebras systems 0.1 to 1 picojoules. The thermodynamic limit, known as Landauer's limit, is k-T times natural log of 2, approximately 3 times 10 to the minus 21 joules at room temperature. Current technology operates 10 to the 9th to 10 to the 10th times above this limit. Cryogenic operation at 4 kelvin reduces k-T by 75 times, enabling superconducting logic like single flux quantum at about 10 to the minus 19 joules per operation, but cooling overhead is significant. On the moon, radiative cooling to 40 kelvin in permanently shadowed craters enables cryogenic operation, and vacuum eliminates moisture issues with cold electronics.

Industry Landscape and Novel Opportunities

E-D-A tools from companies like Synopsys, Cadence, and Siemens provide S-P-I-C-E simulation. T-C-A-D, or technology computer-aided design tools like Sentaurus and Silvaco, simulate device physics. Parameter extraction is critical, using test structures and statistical modeling. Machine learning accelerates development: M-L-based compact models, reinforcement learning for optimization, generative design for novel structures. Key talent is concentrated in Silicon Valley, Taiwan, Korea, and Europe at places like I-M-E-C. Recruiting is challenging but remote work enables distributed teams.

Several novel opportunities exist. Ferroelectric transistors using hafnium-zirconium oxide-based negative capacitance FETs are now manufacturable in CMOS-compatible processes. A startup opportunity exists for specialized foundries targeting ultra-low-power Internet of Things markets. Two-dimensional materials integration has made progress on contact resistance via semi-metal contacts like graphene, or phase engineering of molybdenum disulfide. The opportunity is monolithic three-dimensional integration via low-temperature growth, below 400 degrees Celsius, of two-dimensional FETs on top of CMOS. Chemical vapor deposition scale-up is challenging but M-O-C-V-D suppliers like Aixtron and Veeco can adapt their equipment.

Cryogenic CMOS operation at 77 kelvin offers 100 times lower leakage and 3 times higher mobility. An opportunity exists for co-packaged cryogenic quantum and classical processors—a startup called EeroQ is pursuing this. Western advantage lies in integration with quantum computing efforts at Google, I-B-M, and Rigetti. Challenges include cryocooler efficiency limited by Carnot efficiency and thermal cycling reliability.

Vacuum-packaged chips are motivated by lunar manufacturing but have terrestrial applications. They eliminate moisture, enable higher supply voltages, and remove the need for passivation layers. Hermetic sealing via cold welding—gold-to-gold or copper-to-copper at room temperature in ultra-high vacuum—enables simple packaging. Getter materials maintain vacuum over time. Terrestrial applications include radiation-hard electronics for space and nuclear environments. The challenge is outgassing from organics, necessitating all-inorganic processing.

Photonic-electronic co-integration using silicon photonics for interconnects eliminates R-C delay and reduces power to about 10 femtojoules per bit over 1 millimeter versus 100 femtojoules for electrical interconnects. The opportunity is monolithic laser integration of three-five materials on silicon via template-assisted selective epitaxy. Western strength includes photonic integrated circuit foundries like A-I-M Photonics and Ligentec. In a vacuum fab, direct three-five to silicon bonding is possible without adhesion promoters.

Historical Context and Abandoned Ideas Worth Revisiting

Dennard scaling from 19 74 proposed shrinking dimensions and voltage proportionally to keep power density constant. This ended around 2005 at the 90 nanometer node due to threshold voltage variability and gate leakage, leading to the multicore era. Moore's Law, predicting transistor count doubling every 2 years, is slowing to 3 to 4 years per node, with cost per transistor actually increasing below 7 nanometers. High-k metal gate technology in 2007 at 45 nanometers rescued scaling from gate leakage. FinFET in 20 11 at 22 nanometers addressed short channel effects. E-U-V lithography starting in 20 18 at 7 nanometers simplified patterning. Gate-all-around in 20 24 from Samsung at 3 nanometers, with T-S-M-C at 2 nanometers upcoming, represents the next step.

Josephson junctions for superconducting logic were pursued from the 19 70s to 19 90s by I-B-M and Japan but abandoned due to cryogenic infrastructure costs. It's worth revisiting now that modern cryocoolers are more efficient and quantum computing infrastructure enables shared cryogenics. Rapid single flux quantum, or R-S-F-Q, logic achieves 10 to 100 gigahertz operation at microwatt power levels. An opportunity exists for niche high-performance computing applications and quantum control electronics.

Ballistic transistors using carbon nanotube FETs and three-five high-electron-mobility transistors were abandoned due to integration challenges. Carbon nanotube purification has improved to above 99.9999 percent semiconducting nanotubes via polymer wrapping and density gradient ultracentrifugation. Horizontal alignment via Langmuir-Blodgett techniques is improving. A startup angle could focus on specialized accelerators not requiring full CMOS integration.

Resonant tunneling diodes for multi-valued logic and terahertz oscillators were abandoned for digital logic but are being revisited for analog and R-F applications. Three-five resonant tunneling diodes using indium gallium arsenide and aluminum arsenide demonstrate above 1 terahertz operation. An opportunity exists for wireless interconnect between chiplets.

Molecular electronics with single-molecule FETs were pursued in the 2000s but were premature due to contact reproducibility issues. Modern scanning tunneling microscope lithography and D-N-A origami for molecular placement enable revisiting this approach. Extreme scaling potential below 1 nanometer exists, but commercialization is far off.

Western Fab Strategy

A simplified threshold voltage targeting approach uses body biasing in fully depleted silicon-on-insulator instead of multiple implant splits. STMicroelectronics and GlobalFoundries have 22 and 12 nanometer F-D-S-O-I technology with lower capital expenditure than FinFET. An opportunity exists to license F-D-S-O-I intellectual property targeting Internet of Things and automotive markets that are less demanding than leading-edge.

Vacuum-integrated processing keeps wafers under vacuum from epitaxy through metallization, eliminating cleanrooms for many steps—historically about 30 percent of fab cost. The challenge is vacuum-compatible lithography using electron-beam or nanoimprint instead of optical lithography. Cluster tools from Applied Materials and Tokyo Electron Limited enable multi-chamber vacuum processing that could extend to a full fab. A-I-optimized processes use reinforcement learning for recipe optimization and computer vision for defect detection.

A chiplet-first design avoids leading-edge logic, using mature nodes like 28 nanometers or even 130 nanometers for input-output with advanced packaging. Western strength includes packaging equipment from companies like Kulicke and Soffa and Besi, plus organic substrates from Ajinomoto. Hybrid bonding technology is being developed by Xperi with their D-B-I technology, Intel, and T-S-M-C. An opportunity exists for two-point-five-dimensional and three-dimensional packaging foundries similar to outsourced assembly and test providers but more advanced—Intel Foundry Services is pursuing this.

Cold welding interconnects enable gold-to-gold bonds at less than 1 megapascal pressure at room temperature in vacuum, eliminating reflow ovens, solder, and underfill. This enables reworkable connections. Implementation requires an ultra-high vacuum cluster tool with alignment stage, surface preparation via argon plasma, and bonding head. Robotics accelerates this with parallel bonding of multiple chiplets and automated inspection.

Moon-Specific Insights

The moon's ultra-high vacuum at about 10 to the minus 12 torr natively enables cold welding, eliminates oxidation during processing, and permits high supply voltage operation at 10 to 20 volts versus 0.7 volts on Earth, since breakdown voltage scales with pressure. The challenge is outgassing from implanted hydrogen and organics, requiring all-inorganic processes.

Mineral resources include anorthite for aluminum, ilmenite for titanium and iron, and K-R-E-E-P regions for rare earths. Silicon comes from regolith containing 20 to 45 percent silicon dioxide via carbothermal reduction: silicon dioxide plus 2 carbon yields silicon plus 2 carbon monoxide. Phosphorus and boron for doping must be imported or synthesized via nuclear transmutation, which is impractical. Helium-3 offers future fusion energy. Metal refining uses vacuum carbothermal methods since hydrogen reduction is unavailable without hydrogen gas. Electrorefining in molten salt is energy-intensive.

Passivation-free operation is possible since there's no atmospheric moisture or oxygen, enabling bare metal interconnects of copper or aluminum. This eliminates chemical-mechanical polishing of oxides, reducing process complexity by about 20 steps. Vacuum with dielectric constant of 1 can be used as spacing between conductors with support structures via pillars. Challenges include mechanical rigidity and particle contamination.

Thermal management relies on radiation only, with about 400 kelvin equilibrium at the equator and 40 kelvin in permanently shadowed craters. Active devices at 40 kelvin offer 100 times lower leakage and enable cryogenic operation. The challenge is transient power dissipation, requiring heat pipes to radiators. Regolith provides thermal mass buffering.

AI, Automation, and Research Frontiers

Bayesian optimization for threshold voltage targeting provides 10 to 100 times faster development than design of experiments. Active learning defines process windows. Implementation uses in-line metrology with electrical test structures and closed-loop control. Startups like Instrumental for A-I metrology and Tignis for process control are emerging.

Generative design for transistor structures uses generative adversarial networks and diffusion models for novel geometries. T-C-A-D simulation is a bottleneck, but machine learning surrogate models are 1000 times faster using architectures like PhysNet and DimeNet++. An opportunity exists for A-I-designed gate-all-around nanosheet shapes and optimized source-drain structures.

Robotics already automates wafer handling, but extending to inspection with autonomous T-E-M sample preparation and defect review, plus maintenance with self-healing tools, is possible. Mature robotics enable lights-out fabs where throughput is limited by tool cycle time, not manual intervention. For a lunar fab, teleoperated robotics handle anomaly resolution despite the 2.6 second light delay between Earth and Moon.

Research frontiers include topological insulators for interconnects, where spin-momentum locking reduces scattering. Materials like bismuth selenide and antimony telluride are being integrated with CMOS via molecular beam epitaxy. Technology readiness level is 2 to 3, meaning 10 plus years to production.

Magneto-electric spin-orbit devices are a beyond-CMOS technology using spin-based switching at under 10 millivolts operation. This requires multiferroic materials like bismuth ferrite or lutetium ferrite. Intel partnered with inSpin on this at technology readiness level 3 to 4.

Atomically thin channel FETs using molybdenum disulfide or tungsten diselenide for 1 to 2 nanometer gate length are improving. Contact resistance has improved via phase-engineered contacts and metal-to-semiconductor ohmic contacts using bismuth or tin. Chemical vapor deposition scalability is improving with 4-inch wafers demonstrated. Technology readiness level is 4 to 5, suggesting 5 to 10 years to production.

Probabilistic computing uses stochastic devices like magnetic tunnel junctions and resonant tunneling diodes for Bayesian inference, offering 10 to 100 times energy efficiency for certain workloads. Technology readiness level is 3 to 4, with niche applications appearing first.

Summary

We've covered the deep physics of transistors including threshold voltage, drive current, leakage, on-off ratio, subthreshold slope, short channel effects, D-I-B-L, and gate control. We explored electrical properties like resistance, capacitance, inductance, and especially contact resistance challenges. Performance metrics including clock frequency, transistor density, F-L-O-P-S, memory bandwidth, and latency versus throughput were examined. Power considerations covered dynamic power, static power, and energy per operation with paths toward thermodynamic limits. Industry landscape includes E-D-A and T-C-A-D tools with machine learning acceleration. Novel opportunities span ferroelectric transistors, two-dimensional materials, cryogenic CMOS, vacuum packaging, and photonic integration. Historical context from Dennard scaling to FinFETs to E-U-V and gate-all-around shows the evolution. Abandoned ideas worth revisiting include Josephson junctions, ballistic transistors, resonant tunneling diodes, and molecular electronics. Western fab strategies emphasize F-D-S-O-I, vacuum-integrated processing, chiplet-first design, and cold welding. Lunar manufacturing leverages ultra-high vacuum, mineral resources, passivation-free operation, and cryogenic thermal management. A-I and robotics enable Bayesian optimization, generative design, and lights-out operation. Research frontiers include topological insulators, magneto-electric spin-orbit devices, atomically thin channels, and probabilistic computing. These insights provide the foundation for founding a company in this space and leading technical teams toward novel approaches in semiconductor device physics and electrical engineering.