37 Failure Analysis And Reliability

Failure Analysis and Reliability Core Concepts

Let's dive deep into failure analysis and reliability in semiconductor manufacturing, covering techniques, physics, industry context, and opportunities for innovation. This is essential for anyone building novel chip companies or lunar fabs. We'll start with the core ideas and circle back at the end for reinforcement.

At its heart, failure analysis is detective work on broken chips, and reliability is predicting when chips will break. We use techniques ranging from simple optical microscopy to cutting samples with ion beams and imaging atoms with transmission electron microscopy. Reliability testing accelerates aging by cranking up temperature and voltage to see what fails. The metrics involve failures in time, which is failures per billion device hours, mean time to failure, and statistical distributions like Weibull. The physics includes electromigration where metal atoms move under current stress, time dependent dielectric breakdown where insulators degrade under voltage, negative bias temperature instability in transistors, and hot carrier injection damage.

Failure Analysis Techniques Explained

Let's start with the techniques. Optical microscopy is your first look at a failed device. You're using visible light, so resolution is limited by the Rayleigh criterion to about 200 nanometers. This is cheap, fast, and non-destructive. You can spot obvious surface defects, contamination, and scratches. Tools cost ten thousand to a hundred thousand dollars. But you need better resolution for modern nodes.

That's where scanning electron microscopy comes in, or SEM. You fire a focused electron beam at the sample in vacuum, around ten to the negative six torr. The beam scans across and secondary electrons or backscattered electrons create an image. Secondary electrons show you topography, backscattered show composition because heavier elements scatter more. You get down to one nanometer resolution. These tools run two hundred thousand to a million dollars. There's a specialized mode called voltage contrast where you can see which parts of a circuit are electrically connected by exploiting how the local potential affects secondary electron yield. This is critical for finding shorts and opens in functional devices.

Next level is focused ion beam, or FIB. You use a beam of gallium ions accelerated to thirty kiloelectronvolts to mill away material at nanometer precision. The workflow is to deposit a protective platinum or carbon layer over your region of interest, mill a trench to expose a cross section, then polish the sidewall. Dual beam FIB-SEM systems let you mill and image simultaneously and cost one to two million dollars. The downside is throughput: one to four hours per cross section. And the gallium beam contaminates and damages the sample about ten to twenty nanometers around the cut. There are newer plasma FIBs using xenon that can mill ten to fifty times faster for large volumes.

Transmission electron microscopy, TEM, gives you atomic resolution below point one nanometers. But you need an ultra thin sample, less than a hundred nanometers thick. You prepare these with FIB, mechanical polishing, or ultramicrotomy. The electron beam is accelerated to eighty to three hundred kiloelectronvolts and passes through the sample. You can see the crystal lattice directly, get diffraction patterns for structure, and do elemental analysis with energy dispersive X-ray or electron energy loss spectroscopy. These systems cost two to five million dollars. Sample prep is the bottleneck at four to eight hours per sample.

Delayering is the process of chemically or plasma etching away metal and dielectric layers one by one to access lower levels in the interconnect stack. For aluminum you use acids like nitric, phosphoric, and acetic. For copper you use sulfuric acid and hydrogen peroxide. Or you can use plasma with carbon tetrafluoride and oxygen. This is labor intensive, taking hours to days for advanced nodes, and you risk creating artifacts.

Emission microscopy detects photons emitted from hot spots or shorts in a powered device. The mechanisms are hot carrier luminescence from silicon's bandgap at one point one two electron volts giving eleven hundred nanometer light, or blackbody radiation from resistive heating. You use indium gallium arsenide detectors for near infrared sensitivity and can get sub-micron resolution. There are two variants: OBIRCH, optical beam induced resistance change, scans a laser to heat the device locally and the resulting resistance change maps current paths. TIVA, thermally induced voltage alteration, uses laser induced thermal voltages to find opens and shorts. These are fast, taking minutes, and non-invasive.

Electron beam induced current, EBIC, uses the electron beam to generate electron hole pairs in the semiconductor. The induced current maps electrically active regions like P-N junctions and defects. You need a reverse biased junction. This reveals dopant variations and junction quality.

Reliability Testing Methods

Now let's talk reliability testing. The goal is to accelerate aging so you don't have to wait ten years to see if your chip fails. High temperature operating life, or HTOL, runs devices at one hundred twenty five to one hundred fifty Celsius with nominal or elevated voltage for typically one thousand hours. The Arrhenius equation tells you the acceleration factor: it's exponential in the ratio of inverse temperatures times activation energy over Boltzmann's constant. For silicon devices the activation energy is around point seven electron volts, so a one hundred twenty five Celsius test accelerates by ten to thirty times versus fifty five Celsius operation. The failure mechanisms you're targeting are electromigration, time dependent dielectric breakdown, and package degradation. You test seventy seven to two hundred thirty one units per lot for statistical confidence.

Temperature cycling, or TC, exploits thermal expansion mismatch between materials. You cycle between minus fifty five and plus one hundred twenty five Celsius, five hundred to a thousand cycles, fifteen minute dwells. Silicon's coefficient of thermal expansion is two point six parts per million per kelvin, copper is seventeen, molding compound is fifteen to twenty five. This mismatch drives solder joint fatigue, die cracking, and delamination. The Coffin-Manson relation says cycles to failure goes as delta T to the negative n power where n is two to three.

Highly accelerated stress test, or HAST, combines one hundred thirty Celsius and eighty five percent relative humidity for ninety six to two hundred sixty four hours with electrical bias. It's a pressure cooker environment at two atmospheres. This accelerates corrosion, dendritic growth, and popcorn cracking from moisture absorption. Temperature humidity bias, or THB, is similar but at eighty five Celsius and eighty five percent humidity with one point one times nominal voltage for over a thousand hours. This tests moisture induced failures like electrochemical migration and corrosion.

Electrostatic discharge testing, ESD, checks if the chip can survive a few thousand volt zap from handling. Latchup testing ensures the parasitic thyristor in CMOS structures doesn't trigger under transient currents.

Key Failure Mechanisms

Now the physics. Electromigration, EM, is when electrons carrying current transfer momentum to metal atoms, making them migrate. Voids form at the cathode where atoms deplete, hillocks and extrusions at the anode where they accumulate. Black's equation models mean time to failure as proportional to current density to the negative n power times exponential of activation energy over temperature. The exponent n is one to two, activation energy is point seven to one electron volt for aluminum, point eight to one point two for copper. You test at three hundred to three hundred fifty Celsius and five to ten times nominal current density. Copper damascene process reduced electromigration by about a hundred times versus aluminum due to refractory barriers like tantalum and tantalum nitride and the confined trench geometry.

Time dependent dielectric breakdown, TDDB, happens when electrons tunnel through the gate oxide creating charge traps. Progressive trap generation forms a percolation path leading to breakdown. This is critical for high-k dielectrics like hafnium dioxide. You test with constant voltage stress at one hundred twenty five Celsius, voltage at one point five to two times nominal, until hard breakdown. The time to failure follows a Weibull distribution where the beta shape parameter less than one indicates infant mortality, equal to one is random failures, greater than one is wear out.

Negative bias temperature instability, NBTI, affects PMOS transistors with negative gate bias at elevated temperature. It generates interface traps at the silicon silicon dioxide interface, these are called P-b centers, which shift the threshold voltage. The mechanism is a reaction diffusion model where hydrogen species dissociate from silicon hydrogen bonds and diffuse away. The tricky part is recovery occurs when you remove the bias, so measurement is complicated. You need stress measure stress protocols. Typical shift is about fifty millivolts over ten years. High-k metal gate stacks with hafnium dioxide and titanium nitride improved NBTI.

Hot carrier injection, HCI, happens when carriers gain kinetic energy above silicon's bandgap of one point one two electron volts in high field regions near the drain. This causes impact ionization and creates interface traps. NMOS at gate voltage around half the drain voltage is worst case. Lightly doped drain extensions mitigate field crowding. The lucky electron model describes the probability of injection.

Reliability Metrics and Statistics

For metrics, FIT means failures in time, which is failures per billion device hours. For example, one hundred FIT means one failure per one point one four million years per device, or about one percent failure rate over ten years across a hundred thousand devices. Automotive standards like AEC-Q one hundred require less than one hundred FIT. Data center CPUs target less than ten FIT.

The Weibull distribution models failure times. The cumulative distribution is one minus exponential of negative time over eta to the beta, where eta is characteristic life at sixty three point two percent failure, and beta is the shape parameter. You extract these by plotting log log of one over one minus failure fraction versus log time, which gives a straight line with slope beta.

The Arrhenius equation is fundamental for thermally activated processes. You measure at multiple temperatures to extract activation energy. Typical values are point seven electron volts for silicon diffusion, point nine for copper electromigration, one point two for aluminum oxide time dependent dielectric breakdown.

Common Defect Types

Let's cover defect types. Electrical shorts are unintended connections, often from metal bridging due to inadequate etch, chemical mechanical polishing dishing, or barrier breach. Opens are broken connections from voids in vias, electromigration induced voids, or wire bond failures.

Resistive vias have high resistance vertical connections, usually from incomplete tungsten plug CVD fill, contamination at the interface, or barrier thickness variation. This increases IR drop and local heating leading to runaway failure.

Voids in copper electroplating come from poor seed layer coverage or imbalance in accelerator and suppressor additives. Solder voids come from outgassing or insufficient reflow.

Hillocks and whiskers are stress driven extrusions. Aluminum hillocks form from compressive stress during thermal cycling. Tin whiskers are spontaneous needle like growths from tin plated leads that can bridge conductors, they've caused satellite failures. These are mitigated by tin lead alloy, though that's now restricted by RoHS lead free requirements, or by conformal coatings and annealing.

Delamination is adhesion failure at material interfaces like die to substrate or molding compound. It comes from poor surface prep, moisture ingress, or coefficient of thermal expansion mismatch. You detect it with scanning acoustic microscopy.

Cracks occur when mechanical stress exceeds fracture toughness. Die cracks happen from sawing edge chipping or package warpage. Low-k dielectrics with k less than two point five are mechanically weak, about ten gigapascals elastic modulus versus seventy for silicon dioxide, so they're prone to cracking during chemical mechanical polishing or wire bonding.

Industry Context and Supply Chain

For industry context, specialized vendors dominate. FEI, now part of Thermo Fisher, makes FIB-SEM systems. JEOL makes TEM. DCG Systems, now Onto Innovation, makes emission microscopy tools. Bruker does defect review. Tool costs range from five hundred thousand to five million dollars. Major fabs have centralized failure analysis labs with dozens of tools and twenty to fifty engineers. Third party FA services include EAG, Ansys, and ChipDeLis.

Reliability standards come from JEDEC, like JEP one twenty two for HTOL and JESD twenty two A one oh four for temperature cycling, AEC-Q one hundred for automotive, and MIL-STD-eight eighty three for military. Qualification takes three to six months and costs one to two million dollars per product.

Design for reliability tools are integrated into EDA software. Cadence Virtuoso and Synopsys PrimeTime include electromigration and IR drop checkers, hot carrier injection aging models. Design rules include current density limits below point five milliamps per micron for copper at metal one, via redundancy, and wider wires for critical paths.

Moon Based Manufacturing Considerations

Now for moon based semiconductor manufacturing. The moon's surface pressure is around ten to the negative twelve torr versus ten to the negative nine in a typical vacuum chamber. This eliminates pumpdown time, saving hours per process step, and reduces contamination. Electron and ion beam techniques like SEM, FIB, and TEM operate natively without needing a vacuum system. Emission microscopy benefits because there's no atmospheric absorption or scattering. For TEM you could operate samples in the ambient lunar vacuum without a dedicated chamber, which is a huge simplification.

The lunar thermal environment is extreme. The diurnal cycle is fourteen day day and fourteen day night, from minus one hundred seventy three Celsius at night to plus one hundred twenty seven during the day. That's natural temperature cycling stress testing. However, you need thermal mass and active regulation for stable manufacturing. Passive radiators work more effectively in vacuum for cooling devices during high temperature operating life tests.

There's no moisture on the moon, so HAST and THB tests become irrelevant. Corrosion mechanisms are eliminated. You could skip hermetic packaging for lunar use devices. Reliability simplifies to just electromigration, time dependent dielectric breakdown, negative bias temperature instability, and hot carrier injection.

For materials, lunar regolith is about forty percent oxygen, twenty percent silicon, ten percent aluminum, ten percent calcium. You could extract silicon and aluminum directly. Copper is only trace amounts so it requires import. Iron is available if you want to explore alternatives to gallium for FIB. Water ice at the poles provides hydrogen for plasma etch and wet chemistry.

Running chips in vacuum eliminates air cooling, which challenges thermal management. Radiative cooling scales as temperature to the fourth power by the Stefan Boltzmann law, so you need higher temperatures for adequate heat dissipation. Conduction to heat sinks becomes critical. Vacuum as a dielectric is interesting: the breakdown voltage increases dramatically in ultra high vacuum because you're past the Paschen curve minimum which is around ten to the negative two torr. You could potentially use larger feature sizes with vacuum gaps as insulation, eliminating the need for low-k dielectric deposition and integration. There's no oxidation, so bare copper or aluminum could remain exposed. You don't need passivation layers like silicon nitride or polyimide. However, cold welding is a concern: metals spontaneously weld in ultra high vacuum without the oxide layer. You'd need barriers or controlled surface chemistry to prevent unwanted bonding.

For failure analysis, SEM, FIB, and TEM could operate in the ambient lunar environment. TEM sample prep would be faster without chamber transfers. Emission microscopy could be continuous monitoring without containment. For reliability testing acceleration, the daytime temperature of one hundred twenty seven Celsius enables HTOL without electric ovens. The lunar radiation environment from galactic cosmic rays and solar protons provides natural radiation testing, though that's disruptive for manufacturing.

Building a Competitive Western Fab

For building a competitive western fab, automation is key. AI and machine learning for defect classification in optical and SEM images is a big opportunity. Computer vision with convolutional neural networks trained on labeled defect libraries reduces manual review from hours to minutes. You could automate FIB navigation to defect coordinates from inline inspection, with robotic cross sectioning.

In line reliability monitoring embeds test structures like electromigration stripes and time dependent dielectric breakdown capacitors on every die. You monitor parametric drift during wafer level burn in and predict failures before packaging. This reduces qualification time from months to weeks.

Rapid experimentation uses combinatorial EM and TDDB testing with AI driven design of experiments. You test a matrix of voltage, temperature, and geometry variations on a single wafer. Machine learning models predict lifetime from short term stress. Physics informed neural networks incorporate Black's equation and Arrhenius as constraints, which improves generalization.

Simulation with TCAD tools like Sentaurus and Silvaco models electromigration, hot carrier injection, and negative bias temperature instability. Multiphysics couples electrical, thermal, and mechanical behavior. Computational fluid dynamics models package thermal. A digital twin of the device under stress predicts failure modes before you make silicon. The bottleneck is compute cost: hours to days per simulation. Opportunities include GPU acceleration, reduced order models, and machine learning surrogates.

Chiplets introduce new reliability challenges at the die to die interface. Microbumps with copper pillar and solder are subject to electromigration and temperature cycling fatigue. You need fine pitch interconnect reliability models. Hybrid bonding with direct copper to copper and oxide to oxide eliminates solder for better temperature cycling performance, but requires sub nanometer flatness. Testing is harder because you have to localize failures to a specific die.

Cold welding for interconnects is direct metal to metal bonding without solder or diffusion barriers. Gold to gold or copper to copper in ultra high vacuum or controlled atmosphere like forming gas eliminates intermetallic formation and voids. Lunar ultra high vacuum is ideal. On Earth you need UHV transfer between process steps with vacuum cluster tools. The challenge is surface cleanliness: even a sub monolayer oxide prevents bonding. You can use plasma pre treatment like argon sputtering or load lock integration. The reliability advantage is no electromigration in the bond line because there are no grain boundaries if you form a single crystal contact.

Vacuum packaged devices enclose the chip in vacuum from the wafer level, similar to MEMS packaging. This eliminates moisture and corrosion, enables unpassivated metal, and lets you use vacuum as a dielectric. Getter materials like barium and titanium maintain the vacuum. You need leak rates below ten to the negative twelve atmospheres cubic centimeter per second for decades of hermeticity. Testing uses helium leak detection and residual gas analysis. The added process complexity is wafer bonding, which can be anodic, eutectic, or fusion bonding. Cost is fifty to two hundred dollars per wafer bonding step. This is already done for MEMS inertial sensors and film bulk acoustic resonator filters. The opportunity is extending to logic and memory for extreme reliability environments like space and military.

For talent, failure analysis expertise is concentrated at Intel in Hillsboro and Chandler, Texas Instruments in Dallas, Qualcomm in San Diego, and universities like Stanford, MIT, UT Austin, and NC State. You can recruit from legacy integrated device manufacturers as they shrink. Equipment vendors like Thermo Fisher and JEOL have FA specialists. In Europe, IMEC in Belgium, Fraunhofer in Germany, and CEA-Leti in France are research hubs.

The supply chain for FA tools is mostly US, Japan, and Europe: Thermo Fisher, JEOL, Hitachi, Zeiss. Not China dependent. Consumables include FIB gallium ion sources at about a thousand dollars per year and TEM grids at ten dollars each. Chemicals are standard lab grade. Low geopolitical risk.

For skipping complexity, at mature nodes like twenty eight nanometers and above, optical microscopy plus SEM suffice for eighty percent of failure analysis. TEM is only needed for critical gate oxide and interface issues. You could reduce tool count. For reliability, focusing on intrinsic mechanisms like electromigration and time dependent dielectric breakdown over extrinsic ones like contamination works if your process control is tight. Automotive and datacenter require full qualification, but IoT and consumer can accept higher FIT rates for faster time to market.

Robotics and Automation Opportunities

With mature robotics, sample preparation becomes fully automated. Robotic FIB cross sectioning loads coordinates from CAD, uses automated pattern recognition on alignment marks, and closed loop SEM feedback for endpoint detection. Current systems are semi automated where an operator starts and the robot executes. Future systems could autonomously queue dozens of cross sections overnight. Throughput improves ten to fifty times.

For TEM prep, robots handle mechanical polishing with tripod and wedge methods and automated transfer from FIB to TEM holder loading. Eliminating human handling reduces contamination and breakage.

Delayering becomes robotic wet bench handling through acid baths and rinses. Vision guided defect tracking through layers with automated optical and SEM imaging after each layer removal builds 3D defect reconstruction.

Emission microscopy gets automated probing with needle positioners. Closed loop fault localization detects emission, zooms in, does FIB cross section, TEM prep, and TEM imaging in a fully autonomous failure analysis flow.

For reliability testing, robotic board handling for HTOL ovens and temperature cycling chambers, automated electrical probing with switch matrices and parametric testers, and real time data upload to databases become standard. Mature robotics enables dark reliability labs running twenty four seven without human intervention.

Scaling wise, current FA labs handle one hundred to five hundred samples per month. Full automation gets you to one thousand to five thousand samples per month. Per sample cost drops from five to fifty thousand dollars down to five hundred to five thousand. This enables exhaustive failure analysis of all rejects, not just samples, which improves yield learning.

Historical and Emerging Approaches

Historically, liquid crystals were used for hotspot detection in the nineteen eighties and nineties. You'd spread a liquid crystal film on the die and observe color changes from temperature. This was replaced by emission microscopy for higher resolution and quantitative data.

FIB using gallium liquid metal ion source from the eighties remains standard. Alternatives like helium ions give better resolution with less damage, neon ions balance speed and damage, and xenon plasma FIB offers high throughput.

Real time X-ray imaging at synchrotrons like the Advanced Light Source at Berkeley and ESRF in France demonstrated in situ electromigration void propagation. It wasn't productized due to access and cost. A revival opportunity is compact X-ray sources using inverse Compton scattering.

Approaches abandoned but worth revisiting include superconducting interconnects. Niobium and yttrium barium copper oxide were explored in the nineties. They're electromigration free but require cryogenic operation. Moore's Law prioritized room temperature. Now AI accelerators are exploring cryogenic operation at four kelvin for quantum computing and Josephson junctions. Reliability advantage is zero electromigration, but thermal cycling causes brittleness.

Optical interconnects avoid electromigration entirely. Intel Silicon Photonics succeeded for transceivers but not on chip. The chiplet era could revive this with photonic chiplets for die to die links. Reliability benefits include no metal fatigue, though laser aging and waveguide loss remain issues.

Carbon nanotube interconnects from the twenty tens offer high current capacity at ten to the nine amps per square centimeter versus ten to the six for copper, with ballistic transport. Lab demos succeeded but integration challenges around alignment and contact resistance remain. AI designed growth recipes could enable manufacturability.

Emerging research includes two dimensional materials like graphene and MXenes which are electromigration resistant and atomically thin. Integration via transfer processes is immature. Opportunities include direct synthesis on wafer with CVD or laser assisted transfer.

Self healing dielectrics use polymers with reversible bonds, like Diels-Alder reactions, for time dependent dielectric breakdown mitigation. Healing occurs at the breakdown site. This is academic work at Northwestern and MIT, currently at technology readiness level two to three.

In operando TEM biases chips inside the TEM during imaging for direct observation of electromigration, time dependent dielectric breakdown, and hot carrier injection. Microfabricated TEM holders with electrical feedthroughs are available from companies like Hummingbird Scientific and DENSsolutions. This is at TRL six to seven, with holders costing over a hundred thousand dollars.

Machine learning for Weibull prediction uses small samples, less than ten units, for early failure prediction with Bayesian inference plus physics priors. This could reduce qualification time by ten times and is a startup opportunity.

Atomic layer etching for delayering offers self limiting, damage free layer removal to replace wet chemistry. Lam Research and Tokyo Electron are developing ALE tools at TRL eight to nine for manufacturing, but it's not yet adopted for failure analysis due to cost and throughput.

Quantum sensors using nitrogen vacancy centers in diamond can do magnetic field imaging for current mapping and thermal imaging with sub wavelength resolution. This is academic work at Harvard and Stuttgart at TRL four to five. It could replace emission microscopy.

Novel ideas include electrochemical failure analysis where you apply voltage in an electrolyte to selectively dissolve failed regions via anodic dissolution for rapid defect exposure. This needs chemistry development for etch selectivity and containment in an electrochemical cell.

Acoustic failure analysis uses laser ultrasound with pump probe techniques to detect voids and delamination non destructively with 3D imaging. Rudimentary acoustic microscopy exists. A high resolution version at gigahertz frequencies is feasible with femtosecond lasers.

AI designed accelerated tests use reinforcement learning agents to optimize stress conditions, voltage, temperature, and time, to maximize failure information per test hour. You could personalize stress per device based on inline metrology.

Blockchain for reliability data creates immutable lifetime records across the supply chain from foundry to outsourced assembly and test to original equipment manufacturer. This enables traceability for automotive and liability assignment.

Lunar specific ideas include regolith shielding for radiation hardness by using lunar soil as mass shielding during reliability testing. You get natural heavy ion exposure without an accelerator. Solar thermal HTOL uses concentrated sunlight with parabolic mirrors for one hundred fifty Celsius plus without electrical heaters at zero energy cost. Vacuum brazing for packages does direct metal sealing without solder, avoiding melting point issues in vacuum for high reliability hermetic seals.

Western fab specific ideas include a consortium failure analysis lab, a shared facility for fabless startups to lower the capital barrier. This could follow the NSF funded model like the National Nanotechnology Coordinated Infrastructure for universities but adapted for industry. Open source reliability models would publish Arrhenius and Black's equation parameters that are currently proprietary per foundry. This accelerates design for reliability adoption. An AI foundry for reliability simulation offers cloud based TCAD with pre trained models as a subscription SaaS, lowering the barrier versus hundred thousand dollar plus Synopsys licenses.

Summary of Core Concepts

Let me wrap up by reinforcing the core concepts. Failure analysis uses optical microscopy, SEM, FIB, TEM, delayering, emission microscopy including OBIRCH and TIVA, voltage contrast, and EBIC to dissect failed chips. Reliability testing includes HTOL, temperature cycling, HAST, THB, ESD, latchup, electromigration, time dependent dielectric breakdown, negative bias temperature instability, and hot carrier injection tests. Metrics are FIT, mean time to failure, Weibull distribution, and Arrhenius acceleration. Defects include shorts, opens, resistive vias, voids, hillocks, whiskers, delamination, and cracks.

For the moon, ultra high vacuum simplifies vacuum tools and enables vacuum dielectrics and unpassivated metals. No moisture eliminates corrosion. Natural temperature extremes accelerate testing. Cold welding becomes viable for interconnects.

For western fabs, AI automates defect classification and cross sectioning. In line monitoring predicts failures early. Rapid experimentation with AI driven design of experiments and physics informed neural networks accelerates learning. Chiplets and vacuum packaging are opportunities. Robotics enables dark labs with ten to fifty times throughput.

Historical approaches like superconducting and optical interconnects, carbon nanotubes, and synchrotron X-ray are worth revisiting. Emerging research includes two dimensional materials, self healing dielectrics, in operando TEM, machine learning for Weibull, atomic layer etching, and quantum sensors. Novel ideas include electrochemical and acoustic failure analysis, AI designed tests, and blockchain traceability.Key

terms to remember: FIB for focused ion beam, TEM for transmission electron microscopy, OBIRCH for optical beam induced resistance change, TIVA for thermally induced voltage alteration, EBIC for electron beam induced current, HTOL for high temperature operating life, HAST for highly accelerated stress test, THB for temperature humidity bias, FIT for failures in time, MTTF for mean time to failure, TDDB for time dependent dielectric breakdown, NBTI for negative bias temperature instability, HCI for hot carrier injection, CTE for coefficient of thermal expansion, UHV for ultra high vacuum, TCAD for technology computer aided design, PINN for physics informed neural network, TRL for technology readiness level, and ALE for atomic layer etching.