39 Advanced Topics And Emerging Technologies

Advanced Semiconductor Technologies Core Concepts Review

This overview covers beyond-CMOS devices, advanced interconnects, cutting-edge packaging, quantum computing materials, and photonics integration. Key terms include FinFET, gate-all-around transistors, complementary FETs, tunnel FETs, negative capacitance FETs, spintronics, magnetic RAM, cobalt and ruthenium interconnects, air gaps, backside power delivery, chiplets, 2.5D integration, high-bandwidth memory, hybrid bonding, through-silicon vias, superconducting qubits, cryogenic operation, silicon photonics, and integrated lasers.

Advanced Transistor Architectures Beyond Traditional CMOS

Let's start with the evolution of transistor architectures. The FinFET, introduced by Intel in 20 11 at their 22 nanometer node, represents a fundamental shift from planar transistors to three-dimensional structures. A FinFET uses a vertical silicon fin, typically just 5 to 8 nanometers wide, with the gate wrapping around three sides of this fin. This three-dimensional gate control dramatically improves electrostatic control over the channel, reducing problematic short-channel effects that plague planar devices at small dimensions.

Manufacturing FinFETs requires several sophisticated steps. First, you pattern the fins using self-aligned double or quadruple patterning techniques to achieve the extremely narrow widths required. Then you form shallow trench isolation around the fins, deposit the gate stack conformally around all surfaces, and perform selective epitaxial growth on the fin sidewalls to create the source and drain regions. The critical challenge is maintaining fin width uniformity to within sub-nanometer tolerances while preventing damage during the various etch and deposition steps.

Moving beyond FinFETs, gate-all-around transistors represent the next evolution. Samsung calls their version multi-bridge channel FETs, implemented at their 3 nanometer node. Instead of a fin with three-sided gate coverage, GAA devices use horizontal silicon nanosheets or nanowires completely surrounded by the gate on all four sides. This provides even better electrostatic control and allows designers to tune the nanosheet width independently to optimize for either performance or power efficiency.

The GAA manufacturing process is remarkably complex. You start by growing alternating layers of silicon and silicon-germanium in an epitaxial superlattice structure. After patterning these layers into fin-like shapes, you selectively etch away the silicon-germanium layers to release the silicon nanosheets, leaving them suspended in space. Then you deposit the gate material conformally around all surfaces of these freed nanosheets. This selective release step demands extraordinary etch selectivity and control, as you need to completely remove the SiGe without attacking the silicon channels. TSMC is implementing similar nanosheet technology at their N2 node.

Complementary FETs take vertical integration even further by stacking NMOS transistors above PMOS transistors. This vertical stacking can reduce cell area by roughly 50 percent, a massive improvement in density. However, CFETs present enormous manufacturing challenges. You must form the first transistor layer, add an isolation layer, then either bond a separately processed wafer on top or use monolithic low-temperature processing to build the second transistor layer without degrading the first. Contact formation becomes three-dimensional, requiring vertical connections with sub-nanometer alignment accuracy. Companies like imec and Intel are actively researching CFETs, but they're not yet in production because they require entirely new design methodologies and manufacturing approaches.

Alternative Switching Mechanisms

Tunnel FETs represent a fundamentally different approach to transistor operation. Instead of relying on thermionic emission like conventional MOSFETs, TFETs exploit band-to-band tunneling. The theoretical advantage is substantial: TFETs can achieve subthreshold swings below 60 millivolts per decade, beating the Boltzmann limit that constrains conventional transistors. This would enable ultra-low-power operation. However, despite over 20 years of research, TFETs remain uncommercializedi because their on-current is typically 10 to 100 times lower than CMOS devices. They require extraordinarily steep doping profiles with abruptness below one nanometer, and often demand heterojunctions using materials like germanium or three-five compounds to reduce the tunneling barrier height. The integration complexity has prevented commercialization despite promising characteristics.

Negative capacitance FETs offer another path to sub-60 millivolt per decade switching. These devices incorporate a ferroelectric material, typically hafnium oxide doped with silicon, zirconium, or aluminum, into the gate stack. The ferroelectric exhibits negative capacitance in certain operating regions, which amplifies the surface potential and enables steeper switching. The discovery around 20 11 that hafnium oxide-based materials could show ferroelectric properties was crucial because these materials are CMOS-compatible, unlike traditional ferroelectrics like lead zirconate titanate. Manufacturing requires depositing a thin ferroelectric layer, typically 5 to 10 nanometers, with extremely precise thickness control. Challenges include reliability issues like wake-up effects, fatigue, and imprint, plus fundamental questions about whether the negative capacitance effect is truly quasi-static or only transient. NC-FETs remain in the research phase.

Spintronic Devices and Magnetic Memory

Spintronics exploits electron spin rather than charge for information processing. The most commercially successful spintronic device is MRAM, or magnetic random-access memory. MRAM stores data in magnetic tunnel junctions, which consist of two ferromagnetic layers separated by a thin magnesium oxide tunnel barrier, typically just one nanometer thick. The relative magnetization of these layers, either parallel or antiparallel, determines whether the junction has high or low resistance, representing the one and zero states.

Modern MRAM uses spin-transfer torque for writing, where a spin-polarized current switches the magnetic state. Manufacturing MTJ stacks requires specialized physical vapor deposition equipment from companies like Canon Anelva and Singulus. The critical challenge is achieving defect-free magnesium oxide barriers with precise thickness control to ensure high tunnel magnetoresistance ratios exceeding 200 percent. The entire MTJ stack must be patterned to nanoscale dimensions, then encapsulated to prevent oxidation. Companies like Everspin produce standalone STT-MRAM chips, while Samsung and TSMC offer embedded MRAM in their logic processes.

The advantages of MRAM are compelling: it's non-volatile like Flash but offers nanosecond-scale speed approaching SRAM, endurance exceeding 10 to the 15th cycles, and inherent radiation hardness. The next generation, called SOT-MRAM for spin-orbit torque, uses heavy metals like platinum, tantalum, or tungsten to generate spin currents through the spin Hall effect. This separates the read and write current paths, potentially offering faster switching and better endurance, though it's not yet in production.

For a moon-based semiconductor industry, spintronics offers interesting advantages. The MTJ deposition process already requires ultra-high vacuum, so the lunar environment is naturally compatible. The lack of atmospheric oxygen eliminates oxidation concerns during processing. Additionally, vacuum packaging of spintronic devices, which might be cumbersome on Earth, becomes trivial on the moon.

Advanced Interconnect Materials

As transistors shrink, the metal wires connecting them become problematic. Copper has been the standard interconnect material since the late 1990s, but at dimensions below 20 nanometer pitch, copper's resistivity increases dramatically due to surface scattering and grain boundary effects. This is where alternative materials like cobalt become attractive.

Cobalt has higher bulk resistivity than copper, about 6.2 micro-ohm-centimeters compared to copper's 1.7. However, at small dimensions, cobalt offers several advantages. It can be deposited by chemical vapor deposition with excellent gap-fill and no voids. It forms self-forming barriers with its native oxide and silicide, reducing the thickness of the barrier layer that would otherwise consume a large fraction of the wire's cross-section. TSMC, Samsung, and Intel all use cobalt for the lowest metal layers where dimensions are smallest, while continuing to use copper for upper layers where its superior bulk conductivity dominates.

Ruthenium is another emerging interconnect material, used both as a barrier-liner and potentially as the bulk metal itself. Ruthenium's resistivity of 7.1 micro-ohm-centimeters is lower than tantalum's 13 to 20, and ruthenium barriers can be made thinner, around one nanometer compared to 2 to 3 nanometers for tantalum-tantalum nitride stacks. The challenge with ruthenium is its cost. It trades around 500 to 600 dollars per troy ounce, roughly 100 times more expensive than copper. It also oxidizes readily, requiring careful process control. Companies like Applied Materials and ASM supply the CVD and ALD equipment for ruthenium deposition.

The ultimate low-k dielectric is air itself, with a dielectric constant of exactly one. Air gaps between metal lines dramatically reduce capacitance, lowering RC delay and crosstalk. Intel introduced air gaps at their 14 nanometer node, and TSMC followed at 7 nanometers. The manufacturing process involves depositing a sacrificial material between metal lines, then depositing a sealing layer with an overhang, removing the sacrificial material through small openings, and finally sealing those openings. The challenges include mechanical stability, ensuring the structures can withstand chemical-mechanical polishing, and preventing moisture ingress that could cause reliability problems.

Backside power delivery represents a radical change in chip architecture. Instead of routing power supply rails on the frontside of the wafer, competing with signal routing, you route power on the backside. This requires thinning the wafer to 5 to 10 micrometers, forming nano-through-silicon-vias from the backside to reach the transistors, and building a complete power distribution network on the back. Intel is implementing this as PowerVia in their 20A node in 20 24. The advantages include reduced IR drop, separation of power and signal routing, improved transistor density, and potentially better thermal management. The manufacturing challenges involve handling extremely thin wafers, achieving precise alignment for backside features, and managing the cost of additional processing steps including temporary bonding and debonding.

For a Western fab looking to compete with TSMC, the interconnect space offers opportunities. The specialized CVD and ALD equipment for cobalt and ruthenium deposition is manufactured by U.S. and European companies like Applied Materials, Lam Research, and ASM. The precursor chemistry for these materials is an area where innovation could provide advantages. Companies like Entegris supply these precursors, and there's room for developing better-performing, more stable chemistries. Air gap processing involves significant intellectual property, but alternative approaches to achieving ultra-low-k dielectrics might bypass existing patents.

Advanced Packaging Technologies

Chiplets represent a paradigm shift in semiconductor design. Instead of building a monolithic die with all functions, you disaggregate the design into smaller dies, potentially manufactured on different process nodes or even different technologies, then integrate them using advanced packaging. AMD's EPYC processors use this approach, combining multiple compute chiplets with an I/O die. Intel's Ponte Vecchio GPU uses 47 separate tiles.

The advantages are substantial. Smaller dies have better yield, since a defect kills a smaller piece. You can mix and match technologies, using leading-edge nodes only where necessary and mature, cheaper nodes for I/O and other functions. Time to market improves because different teams can develop chiplets in parallel. However, chiplets introduce challenges. Inter-chiplet communication has higher latency and potentially higher power than on-die connections. Thermal management becomes more complex. And you need a way to test chiplets individually before assembly, requiring known-good-die testing capabilities.

The industry is addressing the standardization challenge with UCIe, the Universal Chiplet Interconnect Express specification, which defines die-to-die interfaces. This enables a chiplet ecosystem where different companies can produce compatible chiplets. For a Western competitor, the chiplet approach offers strategic advantages. It allows focusing resources on leading-edge logic for compute chiplets while using mature nodes or even off-the-shelf components for I/O and memory controllers. The reduced die size improves yield economics, particularly important when bringing up new processes.

2.5D integration uses a silicon interposer, a piece of silicon with through-silicon vias and fine-pitch redistribution layers, as a substrate onto which multiple dies are placed side by side. TSMC's CoWoS, which stands for Chip-on-Wafer-on-Substrate, dominates this market and is used in NVIDIA's A100 and H100 AI accelerators. The interposer allows much finer pitch connections between dies than a traditional organic package substrate, typically 40 to 55 micrometers for the microbumps connecting dies to the interposer, and potentially below 10 micrometers for routing within the interposer.

Intel's EMIB, or Embedded Multi-die Interconnect Bridge, uses small localized silicon bridges instead of a full interposer, reducing cost. The tradeoff is that EMIB only provides high-density connection where the bridge is placed, while CoWoS provides fine-pitch routing across the entire interposer area.

High-bandwidth memory deserves special attention. HBM stacks DRAM dies vertically, typically 4 to 12 high, connected using through-silicon vias. Each stack provides 1024-bit wide interface, enabling bandwidths of 460 to 819 gigabytes per second for HBM2E and HBM3. Manufacturing involves thinning DRAM wafers to about 40 micrometers, forming TSVs, bonding wafers together, then singulating and attaching the resulting stack to a logic die using 2.5D integration. SK Hynix dominates HBM production, with Samsung and Micron also participating. Each HBM stack costs roughly 300 to 600 dollars for 8 to 12 gigabytes.

Hybrid bonding represents the cutting edge of interconnect technology. Instead of using solder bumps or microbumps, hybrid bonding creates direct copper-to-copper and dielectric-to-dielectric bonds. The process requires extraordinary surface preparation: CMP to achieve roughness below 2 nanometers, surface activation with plasma, then precise alignment and pre-bonding at room temperature using van der Waals forces. A subsequent anneal at 200 to 300 degrees Celsius creates permanent covalent bonds between the silicon dioxide layers and enables copper diffusion bonding.

The advantages are dramatic: pitches below 10 micrometers, potentially down to one micrometer, with the lowest possible electrical resistance and capacitance. The challenges are equally dramatic: particles larger than 5 nanometers can cause bonding voids, surface cleanliness is critical, and achieving high yield requires sub-nanometer overlay accuracy. Sony pioneered hybrid bonding for stacked CMOS image sensors, and TSMC offers it as SoIC, System-on-Integrated-Chips, for 3D integration.

For a moon-based fab, hybrid bonding offers particular advantages. The vacuum environment eliminates outgassing concerns during the bonding anneal. The absence of atmospheric moisture prevents contamination that could interfere with bonding. The low-vibration lunar environment could improve alignment accuracy. Additionally, the cold-welding phenomenon, where clean metal surfaces bond at room temperature in vacuum without oxides, might enable simplified bonding approaches.

Quantum Computing Materials

Superconducting qubits are currently the leading approach for quantum computing. These devices use Josephson junctions, which consist of two superconducting electrodes separated by a thin insulating barrier. Niobium, with a critical temperature of 9.3 Kelvin, and aluminum, with a critical temperature of 1.2 Kelvin, are the primary materials. The most common qubit type, the transmon, is essentially an anharmonic LC oscillator where the two lowest energy levels serve as the quantum zero and one states.

Manufacturing superconducting qubits involves depositing thin films of superconductor, typically less than 200 nanometers, using physical vapor deposition. For aluminum junctions, you then perform controlled oxidation to form an aluminum oxide tunnel barrier just 1 to 2 nanometers thick. The oxide thickness determines the junction properties, so precise control is critical. After depositing the second superconductor layer, you pattern the structure using optical or electron-beam lithography and etch.

State-of-the-art superconducting qubits achieve T1 coherence times, which measure energy relaxation, of 100 to 500 microseconds, and T2 times, which measure phase coherence, of 100 to 300 microseconds. Gate fidelities exceed 99.9 percent for single-qubit operations and reach 99 to 99.5 percent for two-qubit gates. These coherence times and fidelities remain the primary limitation for building large-scale quantum computers, as you need roughly 1000 physical qubits per logical qubit with current error rates.

Decoherence, the loss of quantum information, arises from environmental coupling. The primary culprits are lossy dielectrics, two-level systems in amorphous materials, charge noise, flux noise, and nuclear spins in materials. Improving coherence requires materials engineering: using crystalline substrates like silicon or sapphire instead of amorphous silicon dioxide, eliminating lossy dielectrics, and using isotopically purified silicon-28 to remove nuclear spins from silicon-29.

Quantum computers operate at millikelvin temperatures using dilution refrigerators, complex cryogenic systems that cost over a million dollars each. The cooling power at millikelvin temperatures is limited to microwatts, which constrains the number of qubits and the amount of control electronics you can cool. Recent research focuses on cryogenic CMOS, developing control electronics that operate at 4 Kelvin or even millikelvin temperatures, reducing the wiring complexity between temperature stages.

For a moon-based quantum computing facility, several advantages emerge. Passive radiative cooling to deep space at approximately 3 Kelvin significantly reduces the cryogenic refrigeration power requirements. The ultra-high vacuum environment, far better than achievable on Earth, reduces surface adsorbates that create two-level systems causing decoherence. The extremely low vibration environment improves mechanical stability, potentially extending coherence times. The ability to maintain continuous vacuum from fabrication through operation eliminates contamination concerns during transfer.

Photonics Integration

Silicon photonics leverages CMOS manufacturing infrastructure to create optical waveguides and devices in silicon. Silicon has a high refractive index around 3.5, while silicon dioxide cladding has an index around 1.45. This high index contrast enables tight waveguide bends with radii as small as 5 micrometers. Typical single-mode waveguides for 1550 nanometer telecommunications wavelength have dimensions of 450 nanometers width by 220 nanometers height.

Fabrication starts with silicon-on-insulator wafers, uses optical lithography at 193 nanometers or electron-beam lithography for patterning, employs inductively coupled plasma reactive ion etching, then deposits silicon dioxide cladding. Applications include data center interconnects replacing copper cables, LiDAR systems, optical computing, and biosensors. Companies like Intel produce 100 and 400 gigabit transceivers using silicon photonics. AIM Photonics provides foundry services in the United States, while imec and TSMC are developing capabilities.

The fundamental challenge with silicon photonics is that silicon cannot efficiently emit light because it has an indirect bandgap. This requires integrating three-five compound semiconductor lasers. The approaches include flip-chip bonding of separately fabricated InP-based laser dies onto the silicon photonic chip, oxide bonding, or the emerging approach of heteroepitaxial growth. Hybrid integration involves fabricating the laser on its native substrate, then bonding to the silicon chip and coupling the light either evanescently or through butt-coupling.

Modulators convert electrical signals to optical modulation. Silicon photonics modulators use the plasma dispersion effect, where changing carrier concentration in a PN junction modulates the refractive index by 10 to the minus 3rd or minus 4th. Mach-Zehnder interferometer modulators are typically 2 to 5 millimeters long and achieve extinction ratios of 5 to 10 decibels with bandwidth exceeding 50 gigahertz. Ring resonator modulators offer smaller footprints, around 10 micrometer radius, but narrower bandwidth and temperature sensitivity.

Photodetectors complete the optical link by converting received light back to electrical signals. Silicon detects wavelengths shorter than 1100 nanometers, corresponding to its bandgap. For telecommunications wavelengths of 1310 and 1550 nanometers, germanium photodetectors are integrated through selective epitaxial growth on silicon. Despite a 4 percent lattice mismatch between germanium and silicon, careful engineering using graded buffers or defect management techniques achieves responsive photodetectors with responsivity around one amp per watt and bandwidth exceeding 40 gigahertz.

For moon-based photonics, several considerations arise. Operating in vacuum eliminates the need for hermetic packaging to prevent moisture absorption in waveguides. Thermal management becomes simpler with radiative cooling directly to space. The vacuum environment enables better epitaxial growth of germanium photodetectors without oxygen contamination. However, laser thermal management becomes more challenging since radiative cooling is the only mechanism.

For Western fab competitiveness in photonics, the landscape is more favorable than for leading-edge logic. U.S. companies like Intel and startups like Ayar Labs and Lightmatter are competitive. The AIM Photonics foundry provides accessible manufacturing. European institutions like imec and CEA-Leti are strong in photonic integration research. The equipment is largely CMOS-compatible, from U.S. and European suppliers.

Opportunities for Innovation and Novel Approaches

Looking at opportunities for a new Western fab, several areas stand out. For beyond-CMOS devices, GAA transistors and CFETs require new specialized equipment for selective etching and atomic-layer deposition. U.S. companies like Lam Research and Applied Materials supply this equipment. Tunnel FETs and negative capacitance FETs aren't yet commercialized, presenting lower barriers to entry if technical challenges can be overcome.

The chiplet ecosystem offers strategic opportunities. The open UCIe standard enables focusing on specific chiplet types rather than complete systems. Photonic interconnects for chiplets, being developed by companies like Ayar Labs and Lightmatter, could provide bandwidth and power advantages over electrical SerDes. Hybrid bonding for chiplet integration offers the highest performance but requires specialized equipment from companies like EVG and SUSS MicroTec in Europe.

AI-powered experimentation could accelerate development. Machine learning can guide optimization of device structures like GAA nanosheet dimensions, interconnect deposition conditions for cobalt and ruthenium, and hybrid bonding parameters based on surface characterization. Google has demonstrated ML-optimized quantum qubit control pulses. Inverse design using AI can optimize photonic structures. The combination of high-throughput characterization with machine learning enables exploring larger parameter spaces more efficiently than traditional design-of-experiments approaches.

Simulation improvements are critical. Beyond-CMOS devices require quantum transport models using non-equilibrium Green's functions rather than classical drift-diffusion. Tunnel FETs need atomistic tight-binding or density functional theory calculations for accurate tunneling predictions. Spintronics requires micromagnetic simulation combined with spin transport models. At advanced nodes, interconnect simulation must account for electron scattering at surfaces and grain boundaries beyond simple resistivity models. Packaging simulation requires multiphysics coupling of electrical, thermal, and mechanical domains. Physics-informed neural networks offer opportunities to create fast approximate models for co-optimization.

The concept of continuous vacuum processing is compelling. If you can perform multiple process steps without breaking vacuum, you eliminate oxidation between steps, remove the need for some barrier layers, and dramatically reduce pump-down time which currently consumes hours per cycle. For GAA transistors, performing the selective SiGe release in vacuum prevents oxidation that could interfere with subsequent gate deposition. For spintronics, the MTJ stack is already deposited in UHV. For hybrid bonding, performing the entire process in vacuum eliminates outgassing concerns and improves bonding quality.

On the moon, the native ultra-high vacuum environment eliminates the need for vacuum chambers entirely, just enclosures to contain processes. Cold welding of copper in vacuum enables bonding at room temperature without oxide layers, potentially simplifying chiplet interconnection. Quantum computing fabrication through operation in continuous vacuum eliminates contamination and transfer losses. Two-dimensional materials like molybdenum disulfide, which are air-sensitive and degrade on Earth, could be processed and tested in their pristine state.

Historical approaches worth reconsidering include optical computing. In the 1980s, waveguide-based optical logic was extensively researched but abandoned due to integration challenges and lack of suitable light sources. Today's mature silicon photonics manufacturing and integrated lasers might enable optical matrix multiplication for AI accelerators, an approach being commercialized by Lightmatter and Luminous Computing.

Tunnel FETs, explored since the 1990s, might be revived using new heterojunction materials like stacks of two-dimensional semiconductors such as MoS2 and WSe2, or three-five nanowires. Cryogenic CMOS, researched in the 1990s, is being revived for quantum computing control electronics. Vacuum tubes, seemingly obsolete, are being reconsidered as nanoscale vacuum channel transistors offering ballistic transport, radiation hardness, and high-temperature operation.

Entirely novel opportunities include heterogeneous integration of quantum qubits with cryogenic CMOS control on the same package using TSVs for signal routing. Spintronic logic combined with magnetic RAM could enable compute-in-memory architectures eliminating data movement bottlenecks. CFETs combined with buried power rails could achieve maximum density. Topological insulators, if room-temperature versions can be found, might enable dissipationless interconnects through edge states.

Two-dimensional materials beyond graphene offer atomic-scale thickness for ultimate transistor scaling and unique heterojunction properties for tunnel FETs, but integration challenges around transfer versus direct growth remain. Neuromorphic devices using memristors, phase-change memory, or ferroelectric FETs could enable analog computing for AI. Reversible computing using adiabatic logic could achieve ultra-low power if suitable low-dissipation switches like superconductors become practical.

Research frontiers that could reach high technology readiness include room-temperature superconductors, which would revolutionize quantum computing by eliminating cryogenics, though recent claims remain controversial. Majorana fermions for topological qubits offer theoretical protection from decoherence but experimental signatures remain unclear. Diamond nitrogen-vacancy centers for quantum sensing and networking could integrate with silicon photonics for quantum internet applications. Coherent phonon transport for information processing could complement electronics and photonics. Probabilistic computing using stochastic magnetic tunnel junctions shows promise for optimization problems.

For robotics impact, advanced robotics with sub-micron precision could increase chiplet placement throughput by 10 times. Automated handling of thinned wafers for TSV processing could improve yield. Machine learning-guided robotic tuning of quantum qubits could eliminate hours of manual calibration per chip. Robotic fiber alignment for photonics with active feedback could automate currently manual processes. On the moon, teleoperated and autonomous robotics reduce the need for human presence while enabling continuous processing.

Summary of Core Concepts

To summarize, this exploration covered the next generation of transistor architectures beyond traditional CMOS: FinFETs with three-dimensional fins, gate-all-around transistors with complete gate coverage, complementary FETs stacking NMOS and PMOS vertically, tunnel FETs using band-to-band tunneling, and negative capacitance FETs using ferroelectric materials. We examined spintronics and magnetic RAM using magnetic tunnel junctions for non-volatile memory.

Advanced interconnects using cobalt and ruthenium address copper's resistivity problems at small dimensions, while air gaps provide the ultimate low-k dielectric. Backside power delivery and buried power rails optimize chip architecture. Packaging evolution through chiplets, 2.5D integration with silicon interposers, high-bandwidth memory stacks, hybrid bonding, and through-silicon vias enable disaggregated designs and heterogeneous integration.

Quantum computing requires superconducting materials like niobium and aluminum, cryogenic operation at millikelvin temperatures, and careful materials engineering to extend qubit coherence times. Silicon photonics integrates optical waveguides, lasers, modulators, and photodetectors using CMOS manufacturing for data communication and computing applications.

Opportunities for innovation include AI-guided experimentation, improved simulation tools, continuous vacuum processing, cold welding for chiplets, and revival of previously abandoned approaches now enabled by new materials and manufacturing techniques. The moon offers unique advantages through native ultra-high vacuum, low vibrations, radiative cooling, and simplified thermal management. Western fab competitiveness can leverage strengths in equipment, materials, packaging, quantum computing, and photonics while using chiplet architectures to optimize node selection and reduce complexity.