48 Device Design Simulation And Verification

Concepts and Terms

48. Device Design, Simulation, and Verification

TCAD (Technology Computer-Aided Design) Fundamentals

TCAD - Technology Computer-Aided Design; software simulating semiconductor fabrication and device physics
Process simulation - Simulating fabrication steps (implant, diffusion, oxidation, deposition, etch)
Device simulation - Simulating electrical behavior of semiconductor devices
Multiphysics simulation - Coupling electrical, thermal, mechanical, and optical physics
Hierarchical simulation - Linking process → device → circuit simulations
Calibration - Tuning simulation parameters to match experimental data
Predictive simulation - Using physics models to explore new designs before fabrication
Virtual fabrication - Complete process flow simulation before real manufacturing
Design of experiments (DOE) - Systematic variation of parameters to understand sensitivities
Response surface methodology (RSM) - Statistical modeling of simulation results

Process Simulation

Diffusion simulation - Modeling dopant movement at high temperature
Fick's laws - Mathematical description of diffusion (1st: flux, 2nd: concentration change)
Implant simulation - Modeling ion implantation profiles (Monte Carlo or analytical)
Monte Carlo simulation - Statistical particle tracking for implant/etch simulation
BCA (Binary Collision Approximation) - Simplified ion-solid interaction model
Oxidation simulation - Deal-Grove model and extensions
Deposition simulation - Modeling film growth (PVD, CVD, ALD)
Etch simulation - Isotropic, anisotropic, and reactive ion etch modeling
Lithography simulation - Optical and resist exposure modeling
Topography simulation - 2D/3D structure evolution during processing
Level set method - Mathematical technique for tracking moving interfaces
String method - Alternative interface tracking for etch/deposition
Stress simulation - Modeling mechanical stress from process steps
Defect simulation - Modeling point defects, dislocations during processing
Thermal simulation - Temperature distribution during rapid thermal processing

Device Simulation Physics

Drift-diffusion model - Basic transport model (carrier drift + diffusion)
Poisson equation - Relates charge distribution to electric potential
Continuity equations - Conservation of electrons and holes
Mobility model - How carrier mobility depends on field, doping, temperature
Generation-recombination - Carrier creation/destruction mechanisms
SRH (Shockley-Read-Hall) - Trap-assisted recombination model
Auger recombination - Three-particle recombination (important at high injection)
Impact ionization - Carrier multiplication at high electric fields
Tunneling - Quantum mechanical carrier transport through barriers
Band-to-band tunneling (BTBT) - Direct tunneling between bands
Fowler-Nordheim tunneling - Tunneling through triangular barrier
Direct tunneling - Through thin oxide (dominates below ~3nm)
Hot carrier effects - High-energy carriers causing damage or injection
Quantum confinement - Carrier behavior changes in nanoscale dimensions
Density gradient model - Approximate quantum correction to classical transport
Schrödinger equation - Full quantum mechanical carrier description

Advanced Device Simulation

Hydrodynamic model - Includes carrier energy/temperature (beyond drift-diffusion)
Monte Carlo device simulation - Statistical particle tracking (most accurate but slow)
Boltzmann transport equation (BTE) - Fundamental equation for carrier distribution
Non-equilibrium Green's function (NEGF) - Quantum transport for nanoscale devices
Ballistic transport - Carriers traverse device without scattering
Quasi-ballistic - Partial scattering in short-channel devices
Multi-subband transport - Multiple quantum levels in thin channels
Phonon scattering - Lattice vibration interaction with carriers
Coulomb scattering - Carrier-carrier and carrier-impurity interactions
Surface roughness scattering - Interface imperfection effects on mobility
Remote phonon scattering - Phonons in high-k dielectric affecting channel
Self-consistent solution - Iteratively solving coupled equations until convergence
Newton-Raphson method - Numerical technique for solving nonlinear equations
Gummel iteration - Decoupled solution approach for device equations

Compact Modeling

Compact model - Simplified device model for circuit simulation (fast, accurate)
SPICE model - Model format for circuit simulators
BSIM (Berkeley Short-channel IGFET Model) - Industry-standard MOSFET model series
BSIM4 - Widely used model for bulk CMOS
BSIM-CMG - Common multi-gate model for FinFET/GAA
BSIM-IMG - Independent multi-gate model
PSP (Penn State Philips) - Alternative surface-potential-based model
HiSIM - Hiroshima University STARC IGFET Model
EKV model - Charge-based model (good for analog design)
ACM (Advanced Compact MOSFET) - Physics-based model
Surface potential - Key variable in modern compact models
Charge-based modeling - Model based on terminal charges
Threshold voltage modeling - Vt dependence on geometry, bias, temperature
Mobility degradation - Modeling mobility reduction mechanisms
Velocity saturation - Carrier velocity limits at high field
DIBL (Drain-Induced Barrier Lowering) - Short-channel effect in models
Subthreshold conduction - Weak inversion current modeling
Gate leakage model - Tunneling current through gate dielectric
Junction leakage - Reverse-bias diode currents
Noise model - Thermal, flicker (1/f), and shot noise
Mismatch model - Statistical variation between devices
Binning - Using different model parameters for different geometries
Model card - File containing compact model parameters
Model extraction - Determining model parameters from measurements
Model validation - Comparing model predictions to silicon data

Circuit Simulation (SPICE)

SPICE (Simulation Program with Integrated Circuit Emphasis) - Standard circuit simulator
Netlist - Text description of circuit connectivity
DC analysis - Finding steady-state operating point
AC analysis - Small-signal frequency response
Transient analysis - Time-domain simulation
Operating point - DC bias conditions of circuit
Newton-Raphson iteration - Solving nonlinear circuit equations
Convergence - Solution process reaching stable answer
Timestep - Discrete time increment in transient simulation
Adaptive timestep - Automatically adjusting step size
Breakpoints - Times when simulator must evaluate (input transitions)
BSIM tolerance - Accuracy requirements for convergence
Node - Connection point in circuit
Branch - Circuit element between nodes
Modified nodal analysis (MNA) - Matrix formulation for circuit equations
Sparse matrix - Efficient storage for mostly-zero matrices
LU decomposition - Matrix factorization for solving linear systems
Event-driven simulation - Only simulate when signals change (digital-like)

Advanced Circuit Simulation

FastSPICE - Faster simulation using approximations (for large designs)
HSIM - Synopsys hierarchical simulator
FineSim - Synopsys FastSPICE
XA (Extreme Accuracy) - Cadence FastSPICE
Spectre - Cadence high-accuracy analog simulator
HSPICE - Synopsys reference SPICE simulator
PrimeSim - Synopsys next-generation simulator
AMS (Analog Mixed-Signal) simulation - Combined analog and digital
Verilog-A - Analog behavioral modeling language
Verilog-AMS - Mixed analog-digital modeling
IBIS (I/O Buffer Information Specification) - I/O behavioral model standard
Partitioning - Dividing circuit for parallel simulation
Hierarchical simulation - Simulating at multiple abstraction levels
Characterization - Generating timing/power models from SPICE
Golden simulation - Reference simulation for comparison

Monte Carlo and Statistical Simulation

Monte Carlo simulation - Random sampling of parameter variations
Process variation - Manufacturing-induced parameter changes
Local variation - Random differences between nearby devices (mismatch)
Global variation - Systematic differences across die/wafer
Corner analysis - Simulating at process extremes (SS, FF, TT, SF, FS)
SS (Slow-Slow) - Both NMOS and PMOS slow corner
FF (Fast-Fast) - Both NMOS and PMOS fast corner
TT (Typical-Typical) - Nominal process conditions
SF/FS - Skewed corners (one device type fast, other slow)
PVT (Process-Voltage-Temperature) - Three main variation sources
Sigma (σ) - Standard deviation of parameter distribution
3-sigma design - Design works across ±3σ variation (99.7%)
6-sigma design - Design for extreme yields
Worst-case analysis - Conservative design using corner combinations
Statistical timing - Probabilistic timing analysis
SSTA (Statistical Static Timing Analysis) - Statistical version of STA
Yield estimation - Predicting percentage of working chips
Design centering - Optimizing nominal design point for yield

Physical Verification

Physical verification - Checking layout against rules and schematic
Sign-off - Final verification before tapeout
DRC (Design Rule Check) - Verifying layout meets manufacturing rules
LVS (Layout vs. Schematic) - Comparing layout to intended circuit
ERC (Electrical Rule Check) - Checking electrical connectivity rules
DFM (Design for Manufacturability) - Rules improving yield
Antenna rules - Preventing gate oxide damage during fabrication
Density rules - Ensuring uniform pattern density for CMP
Well proximity effect - Modeling threshold shift from nearby wells
LOD (Length of Diffusion) - Stress effect from diffusion edge distance
WPE (Well Proximity Effect) - Threshold variation near well edges
OSE (Oxide Spacing Effect) - STI stress effect on devices

Design Rule Checking (DRC)

Design rule - Geometric constraint for manufacturability
Minimum width - Smallest allowed feature size
Minimum spacing - Smallest gap between features
Enclosure rule - One layer must surround another by minimum amount
Extension rule - Layer must extend beyond another
Overlap rule - Minimum overlap between layers
Via enclosure - Metal must surround via by minimum
Density rule - Minimum/maximum pattern density in window
Slotting rule - Wide metal must have slots (stress relief)
Edge-to-edge spacing - Different from center-to-center (pitch)
Run length - Maximum length of parallel wires
Jog - Offset in wire routing
Notch - Indentation in shape
Acute angle - Sharp angles that are difficult to manufacture
Off-grid - Features not on manufacturing grid
Hierarchical DRC - Checking at cell and top level
Waived violation - Intentionally accepted rule violation
DRC deck - Complete set of design rules for checking

Layout vs. Schematic (LVS)

Device extraction - Identifying transistors from layout shapes
Net extraction - Identifying wire connections
Schematic netlist - Intended circuit connectivity
Layout netlist - Extracted circuit from layout
Comparison - Matching layout netlist to schematic
Short - Unintended connection between nets
Open - Missing connection
Device mismatch - Extracted device differs from schematic
Property mismatch - Device size or parameter differs
Floating node - Net not connected to any driver
Substrate tap - Connection to substrate (required for latchup prevention)
Well tap - Connection to well (required for latchup prevention)
Soft connection - Connection through substrate/well
LVS clean - Layout matches schematic with no errors
LVS BOX - Black-boxed cells (not extracted, assumed correct)
Device recognition layer - Derived layers identifying devices

Parasitic Extraction (PEX)

Parasitic - Unintended R, L, C in layout
RC extraction - Extracting resistance and capacitance
RLC extraction - Including inductance (high frequency)
Coupling capacitance - Capacitance between adjacent wires
Ground capacitance - Capacitance from wire to substrate
Fringe capacitance - Capacitance from wire edges
Wire resistance - Resistance along interconnect
Via resistance - Resistance of vertical connection
Contact resistance - Resistance at metal-to-diffusion interface
Sheet resistance - Resistance per square of layer
Extraction deck - Technology file for extraction rules
SPEF (Standard Parasitic Exchange Format) - File format for parasitics
DSPF (Detailed Standard Parasitic Format) - Detailed parasitic format
Reduced parasitics - Simplified RC network for simulation speed
Lumped model - Single R and C representing distributed network
Distributed model - Multiple RC segments (more accurate)
π-model - C-R-C representation of wire segment
T-model - R/2-C-R/2 representation
Elmore delay - Analytical delay estimate from RC network
AWE (Asymptotic Waveform Evaluation) - Model order reduction technique
Field solver - 3D electromagnetic extraction (most accurate)
Pattern matching - Using pre-characterized patterns (faster)
Quasi-3D extraction - 2.5D approximation (balance of speed/accuracy)

Static Timing Analysis (STA)

STA (Static Timing Analysis) - Exhaustive timing verification without simulation
Timing path - Sequence of logic from input to output
Critical path - Slowest path determining maximum frequency
Setup time - Data must be stable before clock edge
Hold time - Data must be stable after clock edge
Setup violation - Data arrives too late
Hold violation - Data changes too soon after clock
Slack - Margin between required and actual timing
Positive slack - Timing requirement met
Negative slack - Timing violation
TNS (Total Negative Slack) - Sum of all negative slacks
WNS (Worst Negative Slack) - Most critical timing violation
Clock period - Time between clock edges
Clock skew - Difference in clock arrival at different registers
Clock uncertainty - Allowance for clock jitter and variation
Launch clock - Clock edge that launches data
Capture clock - Clock edge that captures data
Data arrival time - When data reaches destination
Data required time - When data must arrive
Timing constraint - Design specification (clock period, I/O timing)
SDC (Synopsys Design Constraints) - Standard format for timing constraints
Multi-corner analysis - Checking timing across PVT corners
Multi-mode analysis - Checking multiple operating modes
MMMC (Multi-Mode Multi-Corner) - Combined analysis approach
OCV (On-Chip Variation) - Timing derating for local variation
AOCV (Advanced OCV) - Path-depth-dependent derating
POCV (Parametric OCV) - Statistical derating
CRPR (Clock Reconvergence Pessimism Removal) - Removing excess pessimism

Timing Characterization

Cell delay - Propagation delay through logic cell
Input slew - Transition time of input signal
Output load - Capacitance driven by output
NLDM (Non-Linear Delay Model) - Table-based delay model
CCS (Composite Current Source) - Current-based timing model
ECSM (Effective Current Source Model) - Cadence current model
Liberty format (.lib) - Standard timing library format
Timing arc - Delay relationship between cell pins
Rise/fall delay - Separate delays for rising/falling edges
Transition time - Time for signal to change (10-90% or 20-80%)
Slew degradation - Transition time increase through cell
Table lookup - Interpolating delay from characterized tables
Delay equation - Analytical delay formula (less common now)

Power Analysis

Dynamic power - Power from switching (P = αCV²f)
Switching activity (α) - Fraction of clock cycles with transitions
Short-circuit power - Power during input transition (both transistors on)
Leakage power - Static power when not switching
Subthreshold leakage - Current when transistor "off"
Gate leakage - Tunneling through gate oxide
Junction leakage - Reverse-bias diode currents
Power grid analysis - IR drop and electromigration checking
VCD (Value Change Dump) - File format for switching activity
SAIF (Switching Activity Interchange Format) - Activity format
Power intent - Specification of power domains and modes
UPF (Unified Power Format) - IEEE standard for power intent
CPF (Common Power Format) - Cadence power format
Power domain - Region with common power supply
Power gating - Turning off power to inactive blocks
Retention - Saving state during power-down

Reliability Analysis

Electromigration (EM) analysis - Current density checking
Current density limit - Maximum allowed J (A/cm²)
Average current - For DC electromigration
RMS current - For AC/switching electromigration
Peak current - Instantaneous maximum
EM rule - Maximum current for given wire width
IR drop analysis - Voltage drop in power grid
Static IR drop - DC voltage drop under average current
Dynamic IR drop - Transient voltage drop during switching
Voltage droop - Temporary voltage reduction under load
Hot spot - Localized high current density
Self-heat analysis - Temperature rise from power dissipation
Thermal analysis - Temperature distribution across chip
MTTF (Mean Time To Failure) - Predicted lifetime
Black's equation - EM lifetime model (MTTF ∝ J⁻ⁿ exp(Ea/kT))
ESD (Electrostatic Discharge) analysis - Protection circuit verification

Formal Verification

Formal verification - Mathematical proof of correctness
Equivalence checking - Proving two designs functionally identical
Model checking - Verifying design properties
Property - Assertion about design behavior
Assertion - Statement that must be true
SVA (SystemVerilog Assertions) - Assertion language
PSL (Property Specification Language) - Alternative assertion language
Bounded model checking - Checking properties up to certain depth
Reachability analysis - Finding all possible states
State space explosion - Exponential growth of states
Abstraction - Simplifying design for verification
Case splitting - Dividing verification into cases
SAT solver - Boolean satisfiability solver (core of formal tools)
BDD (Binary Decision Diagram) - Canonical boolean representation
Cone of influence - Logic affecting specific output

Verification Tools & Software

Calibre (Siemens EDA) - Industry-standard DRC/LVS tool
IC Validator (Synopsys) - Physical verification tool
Pegasus (Cadence) - Physical verification tool
PVS (Cadence) - Physical Verification System
StarRC (Synopsys) - Parasitic extraction tool
QRC (Cadence) - Quantus RC extraction
PrimeTime (Synopsys) - Static timing analysis
Tempus (Cadence) - Static timing analysis
Voltus (Cadence) - Power analysis
PrimePower (Synopsys) - Power analysis
Redhawk (Synopsys) - Power integrity analysis
Totem (Cadence) - Power integrity
Formality (Synopsys) - Equivalence checking
Conformal (Cadence) - Equivalence checking
JasperGold (Cadence) - Formal verification
VC Formal (Synopsys) - Formal verification
Sentaurus (Synopsys) - TCAD suite
Silvaco ATLAS - Device simulation
COMSOL - Multiphysics simulation

Design Flow Integration

Tapeout - Final design submission to foundry
Sign-off - Final verification milestone
ECO (Engineering Change Order) - Late design modification
Metal-only ECO - Change using only metal layers
Functional ECO - Changing logic functionality
Design closure - Achieving all timing/power/DRC goals
Runset - Collection of rule files for verification
Foundry handoff - Delivering design to manufacturing
GDS/GDSII - Layout database format
OASIS - Compressed layout format (replaces GDSII)
LEF/DEF - Library/Design Exchange Formats
OA (OpenAccess) - Database for IC design

Speech Content

Device Design, Simulation, and Verification: A Deep Dive for Semiconductor Founders

Let me introduce the key concepts we will cover: T CAD or Technology Computer-Aided Design, process and device simulation, compact modeling, SPICE circuit simulation, statistical analysis, physical verification including D R C and L V S, parasitic extraction, static timing analysis, power and reliability analysis, and formal verification. We will also explore opportunities for A I acceleration, chiplet architectures, vacuum processing, and lunar manufacturing considerations.

T CAD Fundamentals

T CAD stands for Technology Computer-Aided Design. It is simulation software that models both semiconductor fabrication processes and device physics. The core value proposition is simple: simulate before you fabricate. At advanced nodes, a single mask set costs over ten million dollars, so reducing experimental cycles through simulation is essential.

T CAD operates at multiple levels. Process simulation models the physical and chemical transformations during fabrication, including ion implantation, dopant diffusion, oxidation, deposition, and etching. Device simulation then solves semiconductor physics equations to predict electrical characteristics of the resulting structures. Hierarchical simulation links process to device to circuit, enabling truly predictive design.

Calibration is critical. You must tune fifty to two hundred simulation parameters to match experimental data. Without proper calibration, T CAD predictions are unreliable.

Process Simulation Physics

Diffusion simulation is based on Fick's laws. The first law states that flux is proportional to concentration gradient. The second law describes how concentration evolves over time. In real silicon, diffusion is complex because dopants interact with point defects like vacancies and interstitials. Transient Enhanced Diffusion is particularly important: implant damage creates excess interstitials that can boost diffusion rates by ten to one hundred times.

Implant simulation typically uses Monte Carlo methods, tracking individual ions through the crystal using the Binary Collision Approximation. This treats collisions as sequential two-body events. You need ten thousand to one million ion trajectories for statistical accuracy, taking roughly one second per profile.

Oxidation simulation uses the Deal-Grove model with linear and parabolic regimes. Thin oxides are surface reaction limited while thick oxides are diffusion limited. Extensions handle stress effects and corner geometries.

Etch simulation uses mathematical techniques like the level set method, which tracks interfaces as the zero level of a signed distance function. The string method offers an alternative for complex re-entrant features.

Device Simulation Physics

Device simulation solves three coupled equations self-consistently: the Poisson equation relating charge to potential, and two continuity equations for electrons and holes.

Transport models form a hierarchy of complexity. The drift-diffusion model is fastest, taking seconds for 2D simulations, and works well for devices larger than fifty nanometers. It assumes carriers are in thermal equilibrium with the lattice.

The hydrodynamic model adds carrier temperature equations to capture velocity overshoot and hot carrier effects, running about ten times slower.

Monte Carlo device simulation directly solves the Boltzmann Transport Equation by tracking particles through free flights and scattering events. This is the gold standard for accuracy but runs one thousand times slower than drift-diffusion.

Non-Equilibrium Green's Function methods handle full quantum transport for sub-ten-nanometer devices. They are computationally intensive with cubic scaling in grid points.

Key physics includes mobility models that depend on doping, field, temperature, and stress. Shockley-Read-Hall recombination describes trap-assisted carrier recombination. Auger recombination involves three particles and dominates at high injection. Tunneling mechanisms including band-to-band tunneling, Fowler-Nordheim, and direct tunneling govern leakage in modern devices.

Compact Modeling

Compact models enable circuit simulation of billions of transistors by providing simplified but accurate device equations. SPICE simulation requires models that evaluate in microseconds, not the seconds or minutes of T CAD.

BSIM 4 is the industry workhorse for bulk CMOS with over three hundred parameters. BSIM C M G, the Common Multi-Gate model, handles FinFETs and gate-all-around devices at advanced nodes. P S P from Penn State and Philips is surface-potential-based with better continuity through operating regions.

Model extraction is a bottleneck, typically requiring two to six months per technology node. You measure silicon devices across geometry, bias, and temperature matrices, then extract parameters via optimization algorithms.

Circuit Simulation

SPICE, which stands for Simulation Program with Integrated Circuit Emphasis, originated at Berkeley in 19 73. It solves Modified Nodal Analysis equations using Newton-Raphson iteration for nonlinear systems.

D C analysis finds operating points. A C analysis performs small-signal frequency sweeps. Transient analysis integrates through time using methods like backward Euler or trapezoidal integration.

FastSPICE variants like FineSim and X A trade some accuracy for ten to one hundred times speedup using event-driven simulation and multi-rate timesteps. This enables billion-transistor simulation.

Statistical and Variation Analysis

Process variation includes global effects like wafer-to-wafer differences captured by process corners, and local effects like random dopant fluctuation that require statistical treatment.

Corner analysis simulates at extremes: T T for typical, S S for slow, F F for fast, and skewed corners S F and F S. This is simple but often pessimistic.

Monte Carlo simulation samples parameter distributions across one thousand to ten thousand runs to extract yield statistics. Statistical Static Timing Analysis propagates distributions through timing graphs while capturing path correlations.

Physical Verification

D R C or Design Rule Check verifies that layouts satisfy manufacturing constraints including minimum width, spacing, enclosure, and density rules. Modern rule decks contain over ten thousand rules.

L V S or Layout Versus Schematic verifies that the layout matches the intended circuit by extracting devices and connectivity, then comparing to the schematic netlist.

Key tools include Calibre from Siemens, I C Validator from Synopsys, and Pegasus from Cadence.

Parasitic Extraction

Parasitic extraction captures the resistance, capacitance, and inductance in physical layouts. Field solvers give highest accuracy by solving Maxwell's equations. Pattern matching uses pre-characterized structures for speed. Quasi 3D methods balance accuracy and runtime.

Capacitance includes parallel plate, fringe, and coupling components. At small dimensions, fringe capacitance from edge fields often dominates.

Static Timing Analysis

S T A exhaustively verifies timing without simulation by propagating arrival times through a timing graph. Setup time requires data to arrive before the clock edge. Hold time requires data to remain stable after the clock edge. Slack is the margin between required and actual timing.

On-Chip Variation or O C V provides derating for local variation. Advanced methods like A O C V and P O C V give path-depth and statistically-aware derating.

Opportunities for Innovation

A I-powered T CAD can replace physics solvers with neural network surrogates achieving ten thousand times speedup. Physics-informed neural networks enforce conservation laws while learning from data. Bayesian optimization for design of experiments can reduce experimental iterations by ten times.

Chiplet architectures need new D R C and L V S for die boundaries, cross-die timing analysis, and multi-die power integrity simulation.

Vacuum-resident chip design simplifies many models. With vacuum as dielectric, coupling capacitance drops dramatically. Cold-welded interconnects need new contact resistance models. Continuous vacuum processing eliminates native oxide formation between steps.

For lunar manufacturing, the ultra-high vacuum environment means no oxidation models for exposed surfaces. Thermal simulation becomes critical since only radiation dissipates heat. Radiation effects require single-event and total dose modeling.

Western fab competitiveness benefits from T CAD tools being predominantly American and European. Compact modeling originated at Berkeley. Universities like Stanford, Purdue, T U Wien, and K U Leuven hold key expertise.

Robotics can automate measurement for model extraction, enable high-throughput silicon characterization, and create digital twins with continuous simulation-reality correlation.

Final Review

We covered T CAD for process and device simulation, the physics of diffusion, implantation, oxidation, and etching. We explored device simulation from drift-diffusion through quantum transport methods. Compact models like BSIM enable circuit simulation while S T A provides exhaustive timing verification. Physical verification through D R C and L V S ensures manufacturability. Parasitic extraction captures layout parasitics. Statistical methods handle process variation.

Key opportunities include A I acceleration of simulation, chiplet-specific verification flows, vacuum processing simplification, and novel architectures enabled by keeping devices in vacuum from fabrication through operation. The tools are Western-dominated, talent is accessible at major universities, and significant innovation opportunities exist for entrepreneurs who can combine deep physics understanding with modern A I and automation capabilities.

Technical Overview

TCAD Fundamentals

Technology Computer-Aided Design (TCAD) encompasses simulation software that models semiconductor fabrication processes and device physics. The fundamental value proposition: simulate before fabricating, reducing experimental cycles that cost $10M+ per mask set at advanced nodes.

Core Architecture

Process simulation: Models physical/chemical transformations during fabrication (ion implantation, diffusion, oxidation, deposition, etching, lithography)
Device simulation: Solves semiconductor physics equations (Poisson, continuity, transport) to predict electrical characteristics
Hierarchical simulation: Links process→device→circuit levels, enabling predictive design
Calibration: Critical step matching simulated vs. measured data; typically requires 50-200 parameters adjusted via optimization algorithms

Process Simulation Physics

Diffusion Simulation: Based on Fick's laws:
- First law: J = -D∇C (flux proportional to concentration gradient)
- Second law: ∂C/∂t = D∇²C (concentration evolution)
- Real diffusion in silicon is complex: dopants interact with point defects (vacancies, interstitials), requiring coupled diffusion-reaction models
- Transient Enhanced Diffusion (TED): implant damage creates excess interstitials, boosting diffusion 10-100×

Implant Simulation:
- Monte Carlo methods: Track individual ions through crystal, using Binary Collision Approximation (BCA) for ion-atom interactions
- BCA treats collisions as sequential two-body events, using screened Coulomb potentials (e.g., ZBL potential)
- Generates statistical profiles from 10⁴-10⁶ ion trajectories
- Channeling: ions aligned with crystal axes penetrate deeper; requires crystallographic modeling
- Computational cost: ~1 second per profile for 1M ions

Oxidation Simulation: Deal-Grove model:
- Linear regime: x = (B/A)t (surface reaction limited, thin oxides)
- Parabolic regime: x² = Bt (diffusion limited, thick oxides)
- Extensions handle stress effects, 2D/3D corner effects (bird's beak), and non-planar geometries

Deposition Simulation:
- PVD: Line-of-sight models with angular distribution functions
- CVD: Surface reaction kinetics + gas-phase transport; Knudsen vs. continuum regimes
- ALD: Self-limiting surface chemistry; models predict conformality, GPC (growth per cycle)

Etch Simulation:
- Isotropic: Uniform removal in all directions (wet etch)
- Anisotropic: Directional removal (plasma etch)
- Level set method: Tracks interface as zero-level of signed distance function φ; surface moves according to ∂φ/∂t + v·∇φ = 0
- String method: Alternative tracking using connected boundary points; good for re-entrant features
- RIE modeling requires coupling surface chemistry, ion bombardment, and neutral transport

Lithography Simulation:
- Aerial image: Hopkins' equation for partially coherent imaging
- Resist exposure: Dill's equations for photochemical kinetics
- Development: Mack's model or enhanced Notch model
- OPC simulation: iterative correction to achieve target pattern

Topography Simulation: 2D/3D structure evolution critical for:
- Trench filling (voids, seams)
- Spacer formation
- Contact/via profiles
- Modern challenges: atomic-scale features approaching simulation resolution limits

Device Simulation Physics

Core Equations (self-consistent system):
1. Poisson equation: ∇·(ε∇ψ) = -q(p - n + N_D⁺ - N_A⁻)
2. Electron continuity: ∂n/∂t = (1/q)∇·J_n - R + G
3. Hole continuity: ∂p/∂t = -(1/q)∇·J_p - R + G

Transport Models (hierarchy of complexity/accuracy):

Drift-diffusion: J_n = qμ_n n E + qD_n∇n
Fast (~seconds for 2D), adequate for devices >50nm
Assumes carriers in thermal equilibrium with lattice
Hydrodynamic/Energy transport: Adds carrier temperature equations
Captures velocity overshoot, hot carrier effects
~10× slower than drift-diffusion
Monte Carlo device simulation: Direct solution of Boltzmann Transport Equation via particle tracking
Tracks free flights and scattering events (phonons, impurities, interfaces)
Gold standard for accuracy; ~1000× slower than drift-diffusion
Essential for understanding new materials/devices
Non-Equilibrium Green's Function (NEGF): Full quantum transport
Required for sub-10nm devices, tunneling FETs, quantum dots
Self-energy formalism handles contacts and scattering
Computationally intensive: O(N³) scaling with grid points

Key Physical Models:

Mobility: Depends on doping (ionized impurity scattering), field (velocity saturation: v_sat ≈ 10⁷ cm/s in Si), temperature, stress, interface quality
Shockley-Read-Hall recombination: R_SRH = (np - n_i²)/(τ_p(n + n₁) + τ_n(p + p₁))
Auger recombination: R_Aug = (C_n·n + C_p·p)(np - n_i²) — dominates at high injection
Impact ionization: α, β coefficients for electron/hole multiplication; critical for breakdown
Tunneling: WKB approximation T ≈ exp(-2∫κdx); Band-to-band tunneling (BTBT) limits OFF-state leakage in TFETs; Fowler-Nordheim and direct tunneling govern gate leakage
Quantum confinement: Density gradient method adds quantum potential: U_q ∝ ∇²√n/√n; Full quantum: solve Schrödinger for subbands

Numerical Methods:
- Newton-Raphson: Solves F(x) = 0 via x_{n+1} = x_n - J⁻¹F(x_n)
- Gummel iteration: Decoupled approach; solve Poisson, then n, then p sequentially; more stable but slower convergence
- Scharfetter-Gummel discretization: Stabilizes drift-diffusion on mesh; handles exponential variation across elements
- Typical meshes: 10⁴-10⁶ nodes; adaptive refinement at junctions, interfaces

Compact Modeling

Purpose: Enable circuit simulation of 10⁹+ transistors; device simulation too slow
Requirements: Accuracy (match silicon ±2-5%), physicality (correct derivatives for analog), speed (μs per evaluation), numerical stability

Major Models:
- BSIM4: Industry workhorse for bulk CMOS; threshold-voltage-based; 300+ parameters
- BSIM-CMG (Common Multi-Gate): For FinFETs/GAA; core model for advanced nodes
- PSP: Surface-potential-based; continuous through all regions; favored by some analog designers
- HiSIM: Japanese model; strong physics basis
- EKV: Charge-based; excellent for low-power analog

Model Components:
- Threshold voltage: V_th(L, W, V_BS, V_DS, T) — models short-channel effects (DIBL, Vt roll-off), body effect, temperature
- Mobility: μ_eff accounting for vertical field (surface roughness), lateral field (velocity saturation)
- Current: I_DS = μ_eff·C_ox·(W/L)·f(V_GS, V_DS, V_th) with continuous subthreshold-to-saturation transition
- Capacitances: Gate, overlap, junction capacitances; critical for switching speed
- Leakage: Subthreshold, gate tunneling, junction (GIDL, BTBT)
- Noise: Thermal (4kTgm), flicker (K_f/f), shot

Model Extraction:
- Measure silicon devices across geometry/bias/temperature matrix
- Extract parameters via optimization (gradient descent, genetic algorithms)
- Typically 2-6 months for foundry model card development
- Binning: Different parameters for different geometry bins; up to 1000+ bins at advanced nodes

Circuit Simulation (SPICE)

SPICE (Berkeley, 1973): Solves Modified Nodal Analysis (MNA) equations:
G·V + C·dV/dt = I(t)

Analysis Types:
- DC: Find operating point; Newton-Raphson on nonlinear system
- AC: Small-signal linearization; frequency sweep
- Transient: Time-domain integration (backward Euler, trapezoidal, Gear methods)

Numerical Challenges:
- Convergence: Non-linear devices may not converge; requires good initial guess, limiting, source ramping
- Timestep control: Adaptive timestep based on local truncation error; breakpoints at input transitions
- Matrix solution: LU decomposition; sparse matrix techniques essential (circuits are sparse)

FastSPICE: Trade accuracy for speed
- Event-driven: Only simulate active regions
- Multi-rate: Different timesteps for different partitions
- Table-based: Pre-characterized cells
- 10-100× speedup over SPICE; enables billion-transistor simulation

Key Tools:
- HSPICE (Synopsys): Gold standard accuracy
- Spectre (Cadence): Strong analog features
- PrimeSim, XA, FineSim: FastSPICE variants

Statistical Simulation

Process Variation Sources:
- Global (inter-die): Wafer-to-wafer, lot-to-lot; captured by process corners
- Local (intra-die): Random dopant fluctuation (RDF), line-edge roughness (LER), oxide thickness variation; statistical

Corner Analysis:
- TT (typical), SS (slow NMOS/PMOS), FF (fast), SF, FS
- Simple but pessimistic; may over-constrain design

Monte Carlo:
- Sample parameter distributions (Gaussian, correlated)
- Run N simulations (typically 1000-10000)
- Extract yield statistics
- Challenge: rare events (6σ) require enormous samples or importance sampling

SSTA (Statistical Static Timing Analysis):
- Propagate distributions through timing graph
- Captures correlation between paths
- Enables realistic yield prediction

Physical Verification

DRC (Design Rule Check): Verify layout satisfies manufacturing constraints
- Minimum width, spacing, enclosure, extension, overlap
- Density rules (CMP uniformity)
- Antenna rules (gate oxide protection during etch)
- Modern decks: 10,000+ rules; hierarchical checking essential

LVS (Layout vs. Schematic): Verify layout matches intended circuit
- Extract devices from layout geometry (device recognition)
- Extract connectivity (net extraction)
- Compare to schematic netlist
- Report shorts, opens, mismatches

Key Tools: Calibre (Siemens), IC Validator (Synopsys), Pegasus (Cadence)

Parasitic Extraction (PEX)

Extracts R, C, (L) from physical layout for accurate simulation

Extraction Methods:
- Field solver: Solve Maxwell's equations (Laplace for capacitance); most accurate; slow
- Pattern matching: Use pre-characterized patterns; fast; interpolation for novel geometries
- Quasi-3D: 2D cross-section + coupling; balance of speed/accuracy

Capacitance Components:
- Parallel plate: C = εA/d
- Fringe: Edge fields; dominates at small dimensions
- Coupling: Wire-to-wire; causes crosstalk

Resistance: R = ρL/(W·t); contact/via resistance significant at advanced nodes

Output Formats: SPEF, DSPF for circuit simulation

Tools: StarRC (Synopsys), Quantus/QRC (Cadence)

Static Timing Analysis (STA)

Purpose: Exhaustively verify timing without simulation
- Enumerate all paths: 10¹⁸ paths impossible to simulate
- Graph-based: propagate arrival times through timing graph

Key Concepts:
- Setup: Data must arrive before clock + T_setup
- Hold: Data must remain stable after clock + T_hold
- Slack: Required_time - Arrival_time; positive = pass

Timing Models:
- NLDM: Table of delay vs. (input_slew, output_load)
- CCS/ECSM: Current-source models; better accuracy for nanometer nodes

Variation Handling:
- OCV (On-Chip Variation): Derate cells for local variation
- AOCV/POCV: Depth/statistically-aware derating
- CRPR: Remove pessimism from common clock path

Tools: PrimeTime (Synopsys), Tempus (Cadence)

Power Analysis

Components:
- Dynamic: P = αCV²f (activity × capacitance × voltage² × frequency)
- Short-circuit: Both transistors on during transition
- Leakage: Subthreshold, gate, junction

Analysis Types:
- Average power: From switching activity (VCD/SAIF)
- Peak power: Worst-case instantaneous
- Power grid: IR drop, electromigration

Power Intent: UPF/CPF specify domains, modes, power gating

Reliability Analysis

Electromigration: Current density limits (Black's equation):
MTTF ∝ J⁻ⁿ exp(E_a/kT), n ≈ 1-2, E_a ≈ 0.5-0.9 eV

IR Drop: Voltage drop in power grid
- Static: Average current
- Dynamic: Switching current; can cause timing failures

Self-heating: Especially critical for FinFET/GAA; thermal resistance to substrate higher

Formal Verification

Equivalence Checking: Prove RTL = netlist = layout (post-ECO)
- Uses SAT solvers, BDD-based methods
- Handles 10⁹+ gates

Property Checking: Verify assertions (SVA/PSL)
- Bounded model checking for deep bugs
- Formal proves exhaustively; no coverage gaps

Tools: Formality (Synopsys), Conformal (Cadence), JasperGold (Cadence)

Key TCAD Tools

Process/Device:
- Sentaurus (Synopsys): Industry standard TCAD suite
- Silvaco ATLAS/ATHENA: Strong in compound semiconductors
- COMSOL: General multiphysics; good for MEMS, thermal

Circuit:
- HSPICE, Spectre: Accurate analog simulation
- FastSPICE variants: Full-chip capacity

Verification:
- Calibre, IC Validator, Pegasus: Physical verification
- StarRC, Quantus: Extraction
- PrimeTime, Tempus: Timing
- Voltus, PrimePower: Power

Moon-Specific Considerations

Simulation Advantages:
- Lunar vacuum (10⁻¹² Torr): No oxide growth on exposed surfaces; oxidation models simplified
- Temperature extremes: Require extended thermal simulation ranges
- Reduced gravity: Affects CMP models (slurry behavior); deposition uniformity may change
- No atmospheric contamination: Simplified defect models

Device Operation in Vacuum:
- No moisture-related reliability mechanisms (skip TDDB moisture acceleration models)
- Can simulate devices without passivation layers
- Vacuum as dielectric: ε_r = 1; ultra-low-k implications for parasitic extraction
- Different thermal dissipation (radiation only): Thermal simulation critical; new boundary conditions

Simplified Process Simulation Needs:
- Fewer process steps to model (no wet cleaning, aqueous processes)
- Dry-only etch models; plasma physics more dominant
- Vapor-phase deposition focus (PVD, CVD, ALD)
- Cold welding between metals: New interface models needed

Extraction Implications:
- Vacuum dielectric: C_coupling much lower; relaxed spacing rules
- Different interconnect architecture possible
- Radiation environment: Need to model single-event effects, total ionizing dose

TCAD Opportunities for Lunar Fab:
- Develop specialized models for vacuum-resident devices
- Radiation-hardening-by-design simulation flows
- Thermal management in vacuum (no convection): Detailed FEA integration
- Reduced model complexity: Fewer environmental variables

Western Fab Competitiveness

Current Landscape:
- TCAD tools: Western-dominated (Synopsys, Cadence, Siemens EDA all US/European)
- Compact modeling: Berkeley-originated; universities accessible
- Verification tools: Western incumbents strong

Opportunities:

AI-Powered TCAD:
Replace physics solvers with neural network surrogates (10,000× speedup)
Inverse design: specify targets, AI finds process parameters
Bayesian optimization for DOE: reduce experimental iterations 10×
Physics-informed neural networks (PINNs): enforce conservation laws in ML
Chiplet-Specific Verification:
New DRC/LVS for chiplet boundaries (UCIe, BoW interfaces)
Cross-die timing analysis
Power integrity across chiplet assemblies
Thermal co-simulation of multi-die packages
Vacuum-Resident Chip Design:
Parasitic extraction with vacuum dielectric
No passivation: modified reliability models
Cold-welded interconnects: new contact resistance models
Simplified backend: fewer verification rules
Continuous Vacuum Processing:
Process simulation without atmosphere exposure between steps
No native oxide models needed
Simplified cleaning models
Direct metal-to-metal bonding simulation
Novel Device Architectures:
Vacuum channel transistors: ballistic transport
Cold cathode devices: Fowler-Nordheim emission models
2D material devices: specialized transport models

Talent & Resources:
- TCAD expertise: Stanford, Berkeley, Purdue, TU Wien, KU Leuven
- Compact modeling: Berkeley (BSIM), Penn State (PSP)
- Startups possible in: AI-accelerated simulation, chiplet verification, novel device modeling

Robotics Integration:
- Automated measurement for model extraction
- High-throughput silicon characterization
- Real-time model calibration from manufacturing data
- Digital twin of fab: continuous simulation-reality correlation

Historical & Novel Ideas Worth Revisiting

Abandoned Approaches Now Viable:

Molecular dynamics for process simulation: Too slow historically; GPU/AI acceleration now practical
Full-band Monte Carlo: Required supercomputers; now feasible on workstations
Ab-initio defect modeling: DFT for point defects; informs physics-based models
Behavioral circuit models: ML can now capture complex device behavior without explicit physics

Emerging Research:

Machine Learning Compact Models: Train directly on measurement data; avoid parameter extraction
Differentiable simulation: Backpropagate through physics solvers for optimization
Quantum computing for NEGF: Potential for exponential speedup in quantum transport
Multi-scale simulation: Seamlessly link atomic (DFT) → mesoscale (KMC) → continuum (TCAD)
Stochastic variability simulation: Direct modeling of random discrete dopants, LER
Neuromorphic device models: Memristors, ferroelectrics require new compact model paradigms

Critical Limitations:

TCAD accuracy ceiling: ~10-20% error typical; physics models approximate
Compact model extraction: 3-6 months per technology node; bottleneck for fast iteration
Verification runtime: Advanced-node DRC takes days; full extraction weeks
Corner proliferation: MMMC analysis: 100+ corners; exponential growth

Why Limitations Persist:
- Fundamental physics complexity: Quantum effects, non-equilibrium transport hard to simplify
- Foundry secrecy: Process details hidden; models approximate actual recipes
- Tool integration: Different vendors, formats; data translation loses information
- Scale mismatch: Atomic phenomena govern nm-scale devices; continuum models break down